diff options
| author | aamir <[email protected]> | 2018-06-01 09:52:12 -0700 |
|---|---|---|
| committer | aamir <[email protected]> | 2018-06-01 09:52:12 -0700 |
| commit | e5f532a3b65e17f49991ed08a275f87ac2d68d0a (patch) | |
| tree | 9f6ad33986611788965665592ce35c75faf2c054 | |
| parent | 03de5ae03420ba5666d669c6f76faccf2704fa58 (diff) | |
wmma load working
| -rwxr-xr-x | cuda-kernels/gpgpu_inst_stats.txt | 19 | ||||
| -rw-r--r-- | cuda-kernels/log | 6328 | ||||
| -rw-r--r-- | cuda-kernels/log1 | 512 | ||||
| -rwxr-xr-x | cuda-kernels/tensor_core | bin | 2750968 -> 2750968 bytes | |||
| -rw-r--r-- | src/cuda-sim/Makefile | 2 | ||||
| -rw-r--r-- | src/cuda-sim/cuda-math.h | 1 | ||||
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 2 | ||||
| -rw-r--r-- | src/cuda-sim/half.hpp | 3067 | ||||
| -rw-r--r-- | src/cuda-sim/instructions.cc | 86 | ||||
| -rw-r--r-- | src/cuda-sim/ptx_sim.h | 6 |
10 files changed, 9983 insertions, 40 deletions
diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt index acb1839..41f06a4 100755 --- a/cuda-kernels/gpgpu_inst_stats.txt +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -1 +1,20 @@ kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 164 : 512 2560 1024 0 0 16 16 0 0 +_1.ptx 163 : 512 5696 0 0 0 0 0 0 0 +_1.ptx 162 : 512 5664 0 0 0 0 0 0 0 +_1.ptx 161 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 158 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 156 : 512 134048 2048 0 0 16 16 0 0 +_1.ptx 155 : 512 5632 0 0 0 0 0 0 0 +_1.ptx 154 : 512 5376 0 0 0 0 0 0 0 +_1.ptx 143 : 512 100864 128 0 0 0 0 0 0 +_1.ptx 167 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 144 : 512 100864 0 0 0 0 0 0 0 +_1.ptx 145 : 512 1536 0 0 0 0 0 0 0 +_1.ptx 146 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 147 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 148 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 149 : 512 8384 0 0 0 0 0 0 0 +_1.ptx 150 : 512 4096 0 0 0 0 0 0 0 +_1.ptx 151 : 512 0 0 0 0 0 0 0 0 +_1.ptx 153 : 512 3968 0 0 0 0 0 0 0 diff --git a/cuda-kernels/log b/cuda-kernels/log new file mode 100644 index 0000000..98df26a --- /dev/null +++ b/cuda-kernels/log @@ -0,0 +1,6328 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 40 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " +Parsing file _cuobjdump_complete_output_c7ZC8M +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_70 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 70 + _1.ptx:13 => (ptx_parser.cc:175) start_function + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE + _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) + _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) +GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 + _1.ptx:14 => (ptx_parser.cc:144) init_directive_state + _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc + _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" + _1.ptx:15 => (ptx_parser.cc:219) add_directive + _1.ptx:15 => (ptx_parser.cc:144) init_directive_state + _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 + _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" + _1.ptx:17 => (ptx_parser.cc:219) add_directive + _1.ptx:17 => (ptx_parser.cc:144) init_directive_state + _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE + _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) +GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:319) add_variables + _1.ptx:19 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:175) start_function + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) + _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) + _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" + _1.ptx:22 => (ptx_parser.cc:219) add_directive + _1.ptx:22 => (ptx_parser.cc:144) init_directive_state + _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) + _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" + _1.ptx:23 => (ptx_parser.cc:219) add_directive + _1.ptx:23 => (ptx_parser.cc:144) init_directive_state + _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) + _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" + _1.ptx:24 => (ptx_parser.cc:219) add_directive + _1.ptx:24 => (ptx_parser.cc:144) init_directive_state + _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) + _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" + _1.ptx:25 => (ptx_parser.cc:219) add_directive + _1.ptx:25 => (ptx_parser.cc:144) init_directive_state + _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) + _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" + _1.ptx:26 => (ptx_parser.cc:219) add_directive + _1.ptx:26 => (ptx_parser.cc:144) init_directive_state + _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) + _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" + _1.ptx:27 => (ptx_parser.cc:219) add_directive + _1.ptx:27 => (ptx_parser.cc:144) init_directive_state + _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) + _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" + _1.ptx:28 => (ptx_parser.cc:219) add_directive + _1.ptx:28 => (ptx_parser.cc:144) init_directive_state + _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) + _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" + _1.ptx:30 => (ptx_parser.cc:219) add_directive + _1.ptx:30 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE + _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) +GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 + _1.ptx:32 => (ptx_parser.cc:319) add_variables + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:219) add_directive + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) + _1.ptx:33 => (ptx_parser.cc:319) add_variables + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:219) add_directive + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) + _1.ptx:34 => (ptx_parser.cc:319) add_variables + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:219) add_directive + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) + _1.ptx:35 => (ptx_parser.cc:319) add_variables + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:219) add_directive + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) + _1.ptx:36 => (ptx_parser.cc:319) add_variables + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:219) add_directive + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) + _1.ptx:37 => (ptx_parser.cc:319) add_variables + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:219) add_directive + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) + _1.ptx:38 => (ptx_parser.cc:319) add_variables + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:219) add_directive + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:41 => (ptx_parser.cc:144) init_directive_state + _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:42 => (ptx_parser.cc:144) init_directive_state + _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:43 => (ptx_parser.cc:929) add_address_operand + _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:43 => (ptx_parser.cc:144) init_directive_state + _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:44 => (ptx_parser.cc:929) add_address_operand + _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:44 => (ptx_parser.cc:144) init_directive_state + _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:45 => (ptx_parser.cc:929) add_address_operand + _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:45 => (ptx_parser.cc:144) init_directive_state + _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:46 => (ptx_parser.cc:929) add_address_operand + _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:46 => (ptx_parser.cc:144) init_directive_state + _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:47 => (ptx_parser.cc:929) add_address_operand + _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:47 => (ptx_parser.cc:144) init_directive_state + _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:48 => (ptx_parser.cc:929) add_address_operand + _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:48 => (ptx_parser.cc:144) init_directive_state + _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:50 => (ptx_parser.cc:144) init_directive_state + _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:52 => (ptx_parser.cc:144) init_directive_state + _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:53 => (ptx_parser.cc:144) init_directive_state + _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:54 => (ptx_parser.cc:144) init_directive_state + _1.ptx:55 => (ptx_parser.cc:672) add_option + _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:55 => (ptx_parser.cc:144) init_directive_state + _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:56 => (ptx_parser.cc:144) init_directive_state + _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div + _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:57 => (ptx_parser.cc:144) init_directive_state + _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:58 => (ptx_parser.cc:144) init_directive_state + _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:59 => (ptx_parser.cc:144) init_directive_state + _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:60 => (ptx_parser.cc:144) init_directive_state + _1.ptx:61 => (ptx_parser.cc:672) add_option + _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:61 => (ptx_parser.cc:144) init_directive_state + _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:883) add_literal_int + _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:62 => (ptx_parser.cc:144) init_directive_state + _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:883) add_literal_int + _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:63 => (ptx_parser.cc:144) init_directive_state + _1.ptx:64 => (ptx_parser.cc:672) add_option + _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:64 => (ptx_parser.cc:144) init_directive_state + _1.ptx:65 => (ptx_parser.cc:672) add_option + _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:883) add_literal_int + _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:65 => (ptx_parser.cc:144) init_directive_state + _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:66 => (ptx_parser.cc:144) init_directive_state + _1.ptx:67 => (ptx_parser.cc:672) add_option + _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:67 => (ptx_parser.cc:144) init_directive_state + _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:68 => (ptx_parser.cc:144) init_directive_state + _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:69 => (ptx_parser.cc:889) add_literal_float + _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:69 => (ptx_parser.cc:144) init_directive_state + _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:70 => (ptx_parser.cc:144) init_directive_state + _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:71 => (ptx_parser.cc:144) init_directive_state + _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:72 => (ptx_parser.cc:144) init_directive_state + _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:73 => (ptx_parser.cc:144) init_directive_state + _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:74 => (ptx_parser.cc:144) init_directive_state + _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:75 => (ptx_parser.cc:144) init_directive_state + _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:76 => (ptx_parser.cc:144) init_directive_state + _1.ptx:77 => (ptx_parser.cc:659) add_pred + _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:77 => (ptx_parser.cc:144) init_directive_state + _1.ptx:78 => (ptx_parser.cc:672) add_option + _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:78 => (ptx_parser.cc:144) init_directive_state + _1.ptx:80 => (ptx_parser.cc:643) add_label + _1.ptx:80 => (ptx_parser.cc:295) add_instruction: <label> + _1.ptx:80 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:80 => (ptx_parser.cc:144) init_directive_state + _1.ptx:81 => (ptx_parser.cc:672) add_option + _1.ptx:81 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:81 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:81 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:81 => (ptx_parser.cc:883) add_literal_int + _1.ptx:81 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:81 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:81 => (ptx_parser.cc:144) init_directive_state + _1.ptx:82 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:82 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:82 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:82 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:82 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:82 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:82 => (ptx_parser.cc:144) init_directive_state + _1.ptx:83 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:83 => (ptx_parser.cc:597) add_ptr_spec "global_space" + _1.ptx:83 => (ptx_parser.cc:677) add_option + _1.ptx:83 => (ptx_parser.cc:677) add_option + _1.ptx:83 => (ptx_parser.cc:677) add_option + _1.ptx:83 => (ptx_parser.cc:631) add_scalar_type_spec "F16_TYPE" + _1.ptx:83 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:83 => (ptx_parser.cc:929) add_address_operand + _1.ptx:83 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:83 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:83 => (ptx_parser.cc:295) add_instruction: mma_load + _1.ptx:83 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:83 => (ptx_parser.cc:144) init_directive_state + _1.ptx:84 => (ptx_parser.cc:672) add_option + _1.ptx:84 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:84 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:84 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:84 => (ptx_parser.cc:883) add_literal_int + _1.ptx:84 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:84 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:84 => (ptx_parser.cc:144) init_directive_state + _1.ptx:85 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:85 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:85 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:85 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:85 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:85 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:85 => (ptx_parser.cc:144) init_directive_state + _1.ptx:86 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:86 => (ptx_parser.cc:597) add_ptr_spec "global_space" + _1.ptx:86 => (ptx_parser.cc:677) add_option + _1.ptx:86 => (ptx_parser.cc:677) add_option + _1.ptx:86 => (ptx_parser.cc:677) add_option + _1.ptx:86 => (ptx_parser.cc:631) add_scalar_type_spec "F16_TYPE" + _1.ptx:86 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:86 => (ptx_parser.cc:929) add_address_operand + _1.ptx:86 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:86 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:86 => (ptx_parser.cc:295) add_instruction: mma_load + _1.ptx:86 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:86 => (ptx_parser.cc:144) init_directive_state + _1.ptx:87 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:87 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:87 => (ptx_parser.cc:889) add_literal_float + _1.ptx:87 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:87 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:87 => (ptx_parser.cc:144) init_directive_state + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:88 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:295) add_instruction: mma + _1.ptx:88 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:88 => (ptx_parser.cc:144) init_directive_state + _1.ptx:90 => (ptx_parser.cc:643) add_label + _1.ptx:90 => (ptx_parser.cc:295) add_instruction: <label> + _1.ptx:90 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:90 => (ptx_parser.cc:144) init_directive_state + _1.ptx:91 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:91 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:91 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:91 => (ptx_parser.cc:883) add_literal_int + _1.ptx:91 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:91 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:91 => (ptx_parser.cc:144) init_directive_state + _1.ptx:92 => (ptx_parser.cc:672) add_option + _1.ptx:92 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:92 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:92 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:92 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:92 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:92 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:92 => (ptx_parser.cc:144) init_directive_state + _1.ptx:93 => (ptx_parser.cc:672) add_option + _1.ptx:93 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:93 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:93 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:93 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:93 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:93 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:93 => (ptx_parser.cc:144) init_directive_state + _1.ptx:94 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:94 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:94 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:94 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:94 => (ptx_parser.cc:295) add_instruction: cvt + _1.ptx:94 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:94 => (ptx_parser.cc:144) init_directive_state + _1.ptx:95 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:95 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:95 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:95 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:95 => (ptx_parser.cc:295) add_instruction: cvt + _1.ptx:95 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:95 => (ptx_parser.cc:144) init_directive_state + _1.ptx:96 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:96 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:96 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:96 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:96 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:96 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:96 => (ptx_parser.cc:144) init_directive_state + _1.ptx:97 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:97 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:97 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:97 => (ptx_parser.cc:883) add_literal_int + _1.ptx:97 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:97 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:97 => (ptx_parser.cc:144) init_directive_state + _1.ptx:98 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:98 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:98 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:98 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:98 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:98 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:98 => (ptx_parser.cc:144) init_directive_state + _1.ptx:99 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:99 => (ptx_parser.cc:597) add_ptr_spec "global_space" + _1.ptx:99 => (ptx_parser.cc:677) add_option + _1.ptx:99 => (ptx_parser.cc:677) add_option + _1.ptx:99 => (ptx_parser.cc:677) add_option + _1.ptx:99 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:99 => (ptx_parser.cc:929) add_address_operand + _1.ptx:99 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:99 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:99 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:99 => (ptx_parser.cc:295) add_instruction: mma_store + _1.ptx:99 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:99 => (ptx_parser.cc:144) init_directive_state + _1.ptx:101 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:101 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:101 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:101 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:101 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:101 => (ptx_parser.cc:144) init_directive_state + _1.ptx:103 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:103 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:103 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:103 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:103 => (ptx_parser.cc:295) add_instruction: sub + _1.ptx:103 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:103 => (ptx_parser.cc:144) init_directive_state + _1.ptx:104 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:104 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:104 => (ptx_parser.cc:929) add_address_operand + _1.ptx:104 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:104 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:104 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:104 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:104 => (ptx_parser.cc:144) init_directive_state + _1.ptx:105 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:105 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:105 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:105 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:105 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:105 => (ptx_parser.cc:144) init_directive_state + _1.ptx:106 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:106 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:106 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:106 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:106 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:106 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:106 => (ptx_parser.cc:144) init_directive_state + _1.ptx:108 => (ptx_parser.cc:208) start_instruction_group + _1.ptx:109 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:109 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:109 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:109 => (ptx_parser.cc:381) add_identifier "temp_param_reg" (111) + _1.ptx:109 => (ptx_parser.cc:319) add_variables + _1.ptx:109 => (ptx_parser.cc:144) init_directive_state + _1.ptx:109 => (ptx_parser.cc:219) add_directive + _1.ptx:109 => (ptx_parser.cc:144) init_directive_state + _1.ptx:111 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:111 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:111 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_unclassified scalar_type_spec=B64_TYPE + _1.ptx:111 => (ptx_parser.cc:381) add_identifier "param0" (112) +GPGPU-Sim PTX: allocating stack frame region for .param "param0" from 0x8 to 0x10 + _1.ptx:111 => (ptx_parser.cc:319) add_variables + _1.ptx:111 => (ptx_parser.cc:144) init_directive_state + _1.ptx:111 => (ptx_parser.cc:219) add_directive + _1.ptx:111 => (ptx_parser.cc:144) init_directive_state + _1.ptx:112 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:112 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:112 => (ptx_parser.cc:929) add_address_operand + _1.ptx:112 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:112 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:112 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:112 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:112 => (ptx_parser.cc:144) init_directive_state + _1.ptx:113 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:113 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:113 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_unclassified scalar_type_spec=B64_TYPE + _1.ptx:113 => (ptx_parser.cc:381) add_identifier "param1" (113) +GPGPU-Sim PTX: allocating stack frame region for .param "param1" from 0x10 to 0x18 + _1.ptx:113 => (ptx_parser.cc:319) add_variables + _1.ptx:113 => (ptx_parser.cc:144) init_directive_state + _1.ptx:113 => (ptx_parser.cc:219) add_directive + _1.ptx:113 => (ptx_parser.cc:144) init_directive_state + _1.ptx:114 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:114 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:114 => (ptx_parser.cc:929) add_address_operand + _1.ptx:114 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:114 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:114 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:114 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:114 => (ptx_parser.cc:144) init_directive_state + _1.ptx:115 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:115 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:115 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_unclassified scalar_type_spec=B32_TYPE + _1.ptx:115 => (ptx_parser.cc:381) add_identifier "retval0" (114) +GPGPU-Sim PTX: allocating stack frame region for .param "retval0" from 0x18 to 0x1c + _1.ptx:115 => (ptx_parser.cc:319) add_variables + _1.ptx:115 => (ptx_parser.cc:144) init_directive_state + _1.ptx:115 => (ptx_parser.cc:219) add_directive + _1.ptx:115 => (ptx_parser.cc:144) init_directive_state + _1.ptx:116 => (ptx_parser.cc:672) add_option + _1.ptx:116 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:117 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:119 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:121 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:121 => (ptx_parser.cc:295) add_instruction: call + _1.ptx:121 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:121 => (ptx_parser.cc:144) init_directive_state + _1.ptx:122 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:122 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:122 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:122 => (ptx_parser.cc:929) add_address_operand + _1.ptx:122 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:122 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:122 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:122 => (ptx_parser.cc:144) init_directive_state + _1.ptx:125 => (ptx_parser.cc:213) end_instruction_group + _1.ptx:126 => (ptx_parser.cc:295) add_instruction: ret + _1.ptx:126 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:126 => (ptx_parser.cc:144) init_directive_state + _1.ptx:127 => (ptx_parser.cc:227) end_function + _1.ptx:127 => (ptx_parser.cc:144) init_directive_state + _1.ptx:127 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:127 => (ptx_parser.cc:144) init_directive_state +GPGPU-Sim PTX: instruction assembly for function '_Z12wmma_exampleP6__halfS0_Pfiiiff'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding dominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding postdominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: reconvergence points for _Z12wmma_exampleP6__halfS0_Pfiiiff... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x110 (_1.ptx:77) @!%p5 bra BB0_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x160 (_1.ptx:91) add.u64 %rd8, %SP, 0; +GPGPU-Sim PTX: 2 (potential) branch divergence @ PC=0x118 (_1.ptx:78) bra.uni BB0_1; +GPGPU-Sim PTX: immediate post dominator @ PC=0x120 (_1.ptx:81) mul.wide.s32 %rd4, %r2, 2; +GPGPU-Sim PTX: ... end of reconvergence points for _Z12wmma_exampleP6__halfS0_Pfiiiff +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z12wmma_exampleP6__halfS0_Pfiiiff'. + _1.ptx:127 => (ptx_parser.cc:237) function _Z12wmma_exampleP6__halfS0_Pfiiiff, PC = 0 + + _1.ptx:130 => (ptx_parser.cc:175) start_function + _1.ptx:130 => (ptx_parser.cc:144) init_directive_state + _1.ptx:130 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:130 => (ptx_parser.cc:144) init_directive_state + _1.ptx:130 => (ptx_parser.cc:189) add_function_name _Z17convertFp32ToFp16P6__halfPfi (entrypoint) + _1.ptx:131 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:131 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:131 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:131 => (ptx_parser.cc:381) add_identifier "_Z17convertFp32ToFp16P6__halfPfi_param_0" (115) + _1.ptx:131 => (ptx_parser.cc:577) add_function_arg "_Z17convertFp32ToFp16P6__halfPfi_param_0" + _1.ptx:131 => (ptx_parser.cc:219) add_directive + _1.ptx:131 => (ptx_parser.cc:144) init_directive_state + _1.ptx:132 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:132 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:132 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:132 => (ptx_parser.cc:381) add_identifier "_Z17convertFp32ToFp16P6__halfPfi_param_1" (116) + _1.ptx:132 => (ptx_parser.cc:577) add_function_arg "_Z17convertFp32ToFp16P6__halfPfi_param_1" + _1.ptx:132 => (ptx_parser.cc:219) add_directive + _1.ptx:132 => (ptx_parser.cc:144) init_directive_state + _1.ptx:133 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:133 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:133 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:134 => (ptx_parser.cc:381) add_identifier "_Z17convertFp32ToFp16P6__halfPfi_param_2" (117) + _1.ptx:134 => (ptx_parser.cc:577) add_function_arg "_Z17convertFp32ToFp16P6__halfPfi_param_2" + _1.ptx:134 => (ptx_parser.cc:219) add_directive + _1.ptx:134 => (ptx_parser.cc:144) init_directive_state + _1.ptx:136 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:136 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:136 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:136 => (ptx_parser.cc:381) add_identifier "%p0" (118) + _1.ptx:136 => (ptx_parser.cc:381) add_identifier "%p1" (119) + _1.ptx:136 => (ptx_parser.cc:319) add_variables + _1.ptx:136 => (ptx_parser.cc:144) init_directive_state + _1.ptx:136 => (ptx_parser.cc:219) add_directive + _1.ptx:136 => (ptx_parser.cc:144) init_directive_state + _1.ptx:137 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:137 => (ptx_parser.cc:631) add_scalar_type_spec "B16_TYPE" + _1.ptx:137 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B16_TYPE + _1.ptx:137 => (ptx_parser.cc:381) add_identifier "%rs0" (120) + _1.ptx:137 => (ptx_parser.cc:381) add_identifier "%rs1" (121) + _1.ptx:137 => (ptx_parser.cc:319) add_variables + _1.ptx:137 => (ptx_parser.cc:144) init_directive_state + _1.ptx:137 => (ptx_parser.cc:219) add_directive + _1.ptx:137 => (ptx_parser.cc:144) init_directive_state + _1.ptx:138 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:138 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:138 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:138 => (ptx_parser.cc:381) add_identifier "%f0" (122) + _1.ptx:138 => (ptx_parser.cc:381) add_identifier "%f1" (123) + _1.ptx:138 => (ptx_parser.cc:319) add_variables + _1.ptx:138 => (ptx_parser.cc:144) init_directive_state + _1.ptx:138 => (ptx_parser.cc:219) add_directive + _1.ptx:138 => (ptx_parser.cc:144) init_directive_state + _1.ptx:139 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:139 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:139 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r0" (124) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r1" (125) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r2" (126) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r3" (127) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r4" (128) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r5" (129) + _1.ptx:139 => (ptx_parser.cc:319) add_variables + _1.ptx:139 => (ptx_parser.cc:144) init_directive_state + _1.ptx:139 => (ptx_parser.cc:219) add_directive + _1.ptx:139 => (ptx_parser.cc:144) init_directive_state + _1.ptx:140 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:140 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:140 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd0" (130) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd1" (131) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd2" (132) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd3" (133) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd4" (134) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd5" (135) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd6" (136) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd7" (137) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd8" (138) + _1.ptx:140 => (ptx_parser.cc:319) add_variables + _1.ptx:140 => (ptx_parser.cc:144) init_directive_state + _1.ptx:140 => (ptx_parser.cc:219) add_directive + _1.ptx:140 => (ptx_parser.cc:144) init_directive_state + _1.ptx:143 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:143 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:143 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:143 => (ptx_parser.cc:929) add_address_operand + _1.ptx:143 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:143 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:143 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:143 => (ptx_parser.cc:144) init_directive_state + _1.ptx:144 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:144 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:144 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:144 => (ptx_parser.cc:929) add_address_operand + _1.ptx:144 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:144 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:144 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:144 => (ptx_parser.cc:144) init_directive_state + _1.ptx:145 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:145 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:145 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:145 => (ptx_parser.cc:929) add_address_operand + _1.ptx:145 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:145 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:145 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:145 => (ptx_parser.cc:144) init_directive_state + _1.ptx:146 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:146 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:146 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:146 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:146 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:146 => (ptx_parser.cc:144) init_directive_state + _1.ptx:147 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:147 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:147 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:147 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:147 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:147 => (ptx_parser.cc:144) init_directive_state + _1.ptx:148 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:148 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:148 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:148 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:148 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:148 => (ptx_parser.cc:144) init_directive_state + _1.ptx:149 => (ptx_parser.cc:672) add_option + _1.ptx:149 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:149 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:149 => (ptx_parser.cc:144) init_directive_state + _1.ptx:150 => (ptx_parser.cc:672) add_option + _1.ptx:150 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:150 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:150 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:150 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:150 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:150 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:150 => (ptx_parser.cc:144) init_directive_state + _1.ptx:151 => (ptx_parser.cc:659) add_pred + _1.ptx:151 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:151 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:151 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:151 => (ptx_parser.cc:144) init_directive_state + _1.ptx:153 => (ptx_parser.cc:672) add_option + _1.ptx:153 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:153 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:153 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:153 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:153 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:153 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:153 => (ptx_parser.cc:144) init_directive_state + _1.ptx:154 => (ptx_parser.cc:672) add_option + _1.ptx:154 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:154 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:154 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:154 => (ptx_parser.cc:883) add_literal_int + _1.ptx:154 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:154 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:154 => (ptx_parser.cc:144) init_directive_state + _1.ptx:155 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:155 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:155 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:155 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:155 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:155 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:155 => (ptx_parser.cc:144) init_directive_state + _1.ptx:156 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:156 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:156 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:156 => (ptx_parser.cc:929) add_address_operand + _1.ptx:156 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:156 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:156 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:156 => (ptx_parser.cc:144) init_directive_state + _1.ptx:158 => (ptx_parser.cc:208) start_instruction_group + _1.ptx:158 => (ptx_parser.cc:672) add_option + _1.ptx:158 => (ptx_parser.cc:631) add_scalar_type_spec "F16_TYPE" + _1.ptx:158 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:158 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:158 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:158 => (ptx_parser.cc:295) add_instruction: cvt + _1.ptx:158 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:158 => (ptx_parser.cc:144) init_directive_state + _1.ptx:158 => (ptx_parser.cc:213) end_instruction_group + _1.ptx:161 => (ptx_parser.cc:672) add_option + _1.ptx:161 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:161 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:161 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:161 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:161 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:161 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:161 => (ptx_parser.cc:144) init_directive_state + _1.ptx:162 => (ptx_parser.cc:672) add_option + _1.ptx:162 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:162 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:162 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:162 => (ptx_parser.cc:883) add_literal_int + _1.ptx:162 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:162 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:162 => (ptx_parser.cc:144) init_directive_state + _1.ptx:163 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:163 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:163 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:163 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:163 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:163 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:163 => (ptx_parser.cc:144) init_directive_state + _1.ptx:164 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:164 => (ptx_parser.cc:631) add_scalar_type_spec "U16_TYPE" + _1.ptx:164 => (ptx_parser.cc:929) add_address_operand + _1.ptx:164 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:164 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:164 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:164 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:164 => (ptx_parser.cc:144) init_directive_state + _1.ptx:166 => (ptx_parser.cc:643) add_label + _1.ptx:166 => (ptx_parser.cc:295) add_instruction: <label> + _1.ptx:166 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:166 => (ptx_parser.cc:144) init_directive_state + _1.ptx:167 => (ptx_parser.cc:295) add_instruction: ret + _1.ptx:167 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:167 => (ptx_parser.cc:144) init_directive_state + _1.ptx:168 => (ptx_parser.cc:227) end_function + _1.ptx:168 => (ptx_parser.cc:144) init_directive_state + _1.ptx:168 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:168 => (ptx_parser.cc:144) init_directive_state +GPGPU-Sim PTX: instruction assembly for function '_Z17convertFp32ToFp16P6__halfPfi'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding dominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding postdominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: reconvergence points for _Z17convertFp32ToFp16P6__halfPfi... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x238 (_1.ptx:151) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x288 (_1.ptx:167) ret; +GPGPU-Sim PTX: ... end of reconvergence points for _Z17convertFp32ToFp16P6__halfPfi +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z17convertFp32ToFp16P6__halfPfi'. + _1.ptx:168 => (ptx_parser.cc:237) function _Z17convertFp32ToFp16P6__halfPfi, PC = 504 + +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_VRbcDU" +Running: cat _ptx_VRbcDU | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_7Q1L71 +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_70 -v _ptx2_7Q1L71 --output-file /dev/null 2> _ptx_VRbcDUinfo" +GPGPU-Sim PTX: Kernel '_Z17convertFp32ToFp16P6__halfPfi' : regs=9, lmem=0, smem=0, cmem=372 +GPGPU-Sim PTX: Kernel '_Z12wmma_exampleP6__halfS0_Pfiiiff' : regs=32, lmem=0, smem=0, cmem=396 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_VRbcDU _ptx2_7Q1L71 _ptx_VRbcDUinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: initializing '$str' ... wrote 9 bytes +GPGPU-Sim PTX: finished loading globals (9 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z12wmma_exampleP6__halfS0_Pfiiiff : hostFun 0x0x401cf0, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403730, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039c0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c50, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ee0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404160, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404b60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x405060, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4052e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405500, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405940, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405b60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405d80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405fa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4061c0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4063e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406600, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406820, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406a40, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406c60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406e80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4070a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4072c0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4074e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951c0; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x695200; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x695240; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x695280; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x694580; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1992 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951a0; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x40a6a0; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x40a6c0; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951a8; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x40a6a4; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951b0; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 +GPGPU-Sim PTX: cudaLaunch for 0x0x401dd7 (mode=performance simulation) on stream 0 + 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +GPGPU-Sim PTX: pushing kernel '_Z17convertFp32ToFp16P6__halfPfi' to stream 0, gridDim= (1,1,1) blockDim = (256,1,1) +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z17convertFp32ToFp16P6__halfPfi' +GPGPU-Sim uArch: CTA/core = 8, limited by: threads +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 256, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 0 (ipc= 0.0) sim_rate=0 (inst/sec) elapsed = 0:0:00:01 / Thu May 31 23:09:14 2018 +f2x: 0.000000 +f2x: 1.000000 +f2x: 2.000000 +f2x: 3.000000 +f2x: 4.000000 +f2x: 5.000000 +f2x: 6.000000 +f2x: 7.000000 +f2x: 8.000000 +f2x: 9.000000 +f2x: 10.000000 +f2x: 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data=5bf8 +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1146,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z17convertFp32ToFp16P6__halfPfi'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z17convertFp32ToFp16P6__halfPfi' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z17convertFp32ToFp16P6__halfPfi +kernel_launch_uid = 1 +gpu_sim_cycle = 1147 +gpu_sim_insn = 4608 +gpu_ipc = 4.0174 +gpu_tot_sim_cycle = 1147 +gpu_tot_sim_insn = 4608 +gpu_tot_ipc = 4.0174 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=4608 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 80 + L1I_total_cache_misses = 24 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 24 + L1C_total_cache_misses = 16 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 8 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 16 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 56 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 24 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 4864 +gpgpu_n_tot_w_icount = 152 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 8 +gpgpu_n_mem_write_global = 8 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 256 +gpgpu_n_store_insn = 256 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 768 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:9 W0_Idle:1630 W0_Scoreboard:613 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:152 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 64 {8:8,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 576 {72:8,} +traffic_breakdown_coretomem[INST_ACC_R] = 24 {8:3,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 1088 {136:8,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 64 {8:8,} +traffic_breakdown_memtocore[INST_ACC_R] = 408 {136:3,} +maxmrqlatency = 18 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 255 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 1146 +mrq_lat_table:16 0 4 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 5 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 24/15 = 1.600000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 8 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 252 254 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none none none none none none 0 +dram[6]: none none none none none none none none none none none none none none 0 0 +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 254 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2123 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003759 +n_activity=40 dram_eff=0.2 +bk0: 4a 2109i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 0a 2128i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2104i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2103i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2104i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2104i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2123 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003759 +n_activity=40 dram_eff=0.2 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 4a 2109i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=80 dram_eff=0.2 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2129i bk14: 4a 2109i bk15: 4a 2108i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2128 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2128i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 0a 2128i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2128 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2128i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 0a 2128i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2110 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.01504 +n_activity=75 dram_eff=0.4267 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2067i bk11: 4a 2074i bk12: 0a 2126i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.037594 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2110 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.01504 +n_activity=73 dram_eff=0.4384 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2069i bk11: 4a 2073i bk12: 0a 2126i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0390038 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 20 +L2_total_cache_misses = 16 +L2_total_cache_miss_rate = 0.8000 +L2_total_cache_pending_hits = 4 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 8 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 4 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 4 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.003 + +icnt_total_pkts_mem_to_simt=66 +icnt_total_pkts_simt_to_mem=36 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 8.5 + minimum = 6 + maximum = 20 +Network latency average = 8.5 + minimum = 6 + maximum = 20 +Slowest packet = 20 +Flit latency average = 7.78431 + minimum = 6 + maximum = 16 +Slowest flit = 54 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.000281484 + minimum = 0 (at node 0) + maximum = 0.008726 (at node 1) +Accepted packet rate average = 0.000281484 + minimum = 0 (at node 0) + maximum = 0.008726 (at node 1) +Injected flit rate average = 0.000717784 + minimum = 0 (at node 0) + maximum = 0.0157068 (at node 1) +Accepted flit rate average= 0.000717784 + minimum = 0 (at node 0) + maximum = 0.0287958 (at node 1) +Injected packet length average = 2.55 +Accepted packet length average = 2.55 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 4608 (inst/sec) +gpgpu_simulation_rate = 1147 (cycle/sec) + +GPGPU-Sim PTX: cudaLaunch for 0x0x401dd7 (mode=performance simulation) on stream 0 +GPGPU-Sim PTX: pushing kernel '_Z17convertFp32ToFp16P6__halfPfi' to stream 0, gridDim= (1,1,1) blockDim = (256,1,1) +GPGPU-Sim uArch: Shader 2 bind to kernel 2 '_Z17convertFp32ToFp16P6__halfPfi' +GPGPU-Sim uArch: core: 2, cta: 0, start_tid: 0, end_tid: 256, initialized @(1,1147) +f2x: 0.000000 +f2x: 1.000000 +f2x: 2.000000 +f2x: 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data=5bd8 +st:addr=3e20bf8 data=5be0 +st:addr=3e20bfa data=5be8 +st:addr=3e20bfc data=5bf0 +st:addr=3e20bfe data=5bf8 +GPGPU-Sim uArch: Shader 2 finished CTA #0 (909,1147), 0 CTAs running +GPGPU-Sim uArch: Shader 2 empty (last released kernel 2 '_Z17convertFp32ToFp16P6__halfPfi'). +GPGPU-Sim uArch: GPU detected kernel 2 '_Z17convertFp32ToFp16P6__halfPfi' finished on shader 2. +Destroy streams for kernel 2: size 0 +kernel_name = _Z17convertFp32ToFp16P6__halfPfi +kernel_launch_uid = 2 +gpu_sim_cycle = 910 +gpu_sim_insn = 4608 +gpu_ipc = 5.0637 +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 246 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 8.75 + minimum = 6 + maximum = 22 +Network latency average = 8.75 + minimum = 6 + maximum = 22 +Slowest packet = 60 +Flit latency average = 8.35294 + minimum = 6 + maximum = 18 +Slowest flit = 156 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.000354874 + minimum = 0 (at node 0) + maximum = 0.0110011 (at node 2) +Accepted packet rate average = 0.000354874 + minimum = 0 (at node 0) + maximum = 0.0110011 (at node 2) +Injected flit rate average = 0.000904929 + minimum = 0 (at node 0) + maximum = 0.019802 (at node 2) +Accepted flit rate average= 0.000904929 + minimum = 0 (at node 0) + maximum = 0.0363036 (at node 2) +Injected packet length average = 2.55 +Accepted packet length average = 2.55 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 9216 (inst/sec) +gpgpu_simulation_rate = 2057 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 250 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 250 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 +M = 16, N = 16, K = 16. alpha = 1.000000, beta = 1.000000 + +Running with wmma... + 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Network latency average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Flit latency average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Fragmentation average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Injected packet rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Accepted packet rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Injected flit rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Accepted flit rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Injected packet size average = -nan (6 samples) +Accepted packet size average = -nan (6 samples) +Hops average = -nan (6 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + +GPGPU-Sim PTX: cudaLaunch for 0x0x401cf0 (mode=performance simulation) on stream 0 + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 +GPGPU-Sim PTX: pushing kernel '_Z12wmma_exampleP6__halfS0_Pfiiiff' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 250 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Network latency average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Flit latency average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Fragmentation average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Injected packet rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Accepted packet rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Injected flit rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Accepted flit rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Injected packet size average = -nan (7 samples) +Accepted packet size average = -nan (7 samples) +Hops average = -nan (7 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 3 bind to kernel 3 '_Z12wmma_exampleP6__halfS0_Pfiiiff' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 3, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,2057) +mma_ld: thrd=0,addr=65144832, fp16(size=16), stride=16 +thread0=0,3c00,4000,4200,4400,4500,4600,4700 +mma_ld: thrd=1,addr=65144832, fp16(size=16), stride=16 +thread0=4800,4880,4900,4980,4a00,4a80,4b00,4b80 +mma_ld: thrd=2,addr=65144832, fp16(size=16), stride=16 +thread0=4c00,4c40,4c80,4cc0,4d00,4d40,4d80,4dc0 +mma_ld: thrd=3,addr=65144832, fp16(size=16), stride=16 +thread0=4e00,4e40,4e80,4ec0,4f00,4f40,4f80,4fc0 +mma_ld: thrd=4,addr=65144832, fp16(size=16), stride=16 +thread0=5000,5020,5040,5060,5080,50a0,50c0,50e0 +mma_ld: thrd=5,addr=65144832, fp16(size=16), stride=16 +thread0=5100,5120,5140,5160,5180,51a0,51c0,51e0 +mma_ld: thrd=6,addr=65144832, fp16(size=16), stride=16 +thread0=5200,5220,5240,5260,5280,52a0,52c0,52e0 +mma_ld: thrd=7,addr=65144832, fp16(size=16), stride=16 +thread0=5300,5320,5340,5360,5380,53a0,53c0,53e0 +mma_ld: thrd=8,addr=65144832, fp16(size=16), stride=16 +thread0=5400,5410,5420,5430,5440,5450,5460,5470 +mma_ld: thrd=9,addr=65144832, fp16(size=16), stride=16 +thread0=5480,5490,54a0,54b0,54c0,54d0,54e0,54f0 +mma_ld: thrd=10,addr=65144832, fp16(size=16), stride=16 +thread0=5500,5510,5520,5530,5540,5550,5560,5570 +mma_ld: thrd=11,addr=65144832, fp16(size=16), stride=16 +thread0=5580,5590,55a0,55b0,55c0,55d0,55e0,55f0 +mma_ld: thrd=12,addr=65144832, fp16(size=16), stride=16 +thread0=5600,5610,5620,5630,5640,5650,5660,5670 +mma_ld: thrd=13,addr=65144832, fp16(size=16), stride=16 +thread0=5680,5690,56a0,56b0,56c0,56d0,56e0,56f0 +mma_ld: thrd=14,addr=65144832, fp16(size=16), stride=16 +thread0=5700,5710,5720,5730,5740,5750,5760,5770 +mma_ld: thrd=15,addr=65144832, fp16(size=16), stride=16 +thread0=5780,5790,57a0,57b0,57c0,57d0,57e0,57f0 +mma_ld: thrd=16,addr=65144832, fp16(size=16), stride=16 +thread0=5800,5808,5810,5818,5820,5828,5830,5838 +mma_ld: thrd=17,addr=65144832, fp16(size=16), stride=16 +thread0=5840,5848,5850,5858,5860,5868,5870,5878 +mma_ld: thrd=18,addr=65144832, fp16(size=16), stride=16 +thread0=5880,5888,5890,5898,58a0,58a8,58b0,58b8 +mma_ld: thrd=19,addr=65144832, fp16(size=16), stride=16 +thread0=58c0,58c8,58d0,58d8,58e0,58e8,58f0,58f8 +mma_ld: thrd=20,addr=65144832, fp16(size=16), stride=16 +thread0=5900,5908,5910,5918,5920,5928,5930,5938 +mma_ld: thrd=21,addr=65144832, fp16(size=16), stride=16 +thread0=5940,5948,5950,5958,5960,5968,5970,5978 +mma_ld: thrd=22,addr=65144832, fp16(size=16), stride=16 +thread0=5980,5988,5990,5998,59a0,59a8,59b0,59b8 +mma_ld: thrd=23,addr=65144832, fp16(size=16), stride=16 +thread0=59c0,59c8,59d0,59d8,59e0,59e8,59f0,59f8 +mma_ld: thrd=24,addr=65144832, fp16(size=16), stride=16 +thread0=5a00,5a08,5a10,5a18,5a20,5a28,5a30,5a38 +mma_ld: thrd=25,addr=65144832, fp16(size=16), stride=16 +thread0=5a40,5a48,5a50,5a58,5a60,5a68,5a70,5a78 +mma_ld: thrd=26,addr=65144832, fp16(size=16), stride=16 +thread0=5a80,5a88,5a90,5a98,5aa0,5aa8,5ab0,5ab8 +mma_ld: thrd=27,addr=65144832, fp16(size=16), stride=16 +thread0=5ac0,5ac8,5ad0,5ad8,5ae0,5ae8,5af0,5af8 +mma_ld: thrd=28,addr=65144832, fp16(size=16), stride=16 +thread0=5b00,5b08,5b10,5b18,5b20,5b28,5b30,5b38 +mma_ld: thrd=29,addr=65144832, fp16(size=16), stride=16 +thread0=5b40,5b48,5b50,5b58,5b60,5b68,5b70,5b78 +mma_ld: thrd=30,addr=65144832, fp16(size=16), stride=16 +thread0=5b80,5b88,5b90,5b98,5ba0,5ba8,5bb0,5bb8 +mma_ld: thrd=31,addr=65144832, fp16(size=16), stride=16 +thread0=5bc0,5bc8,5bd0,5bd8,5be0,5be8,5bf0,5bf8 +mma_ld: thrd=0,addr=65145344, fp16(size=16), stride=16 +thread0=0,3c00,4000,4200,4400,4500,4600,4700 +mma_ld: thrd=1,addr=65145344, fp16(size=16), stride=16 +thread0=4800,4880,4900,4980,4a00,4a80,4b00,4b80 +mma_ld: thrd=2,addr=65145344, fp16(size=16), stride=16 +thread0=4c00,4c40,4c80,4cc0,4d00,4d40,4d80,4dc0 +mma_ld: thrd=3,addr=65145344, fp16(size=16), stride=16 +thread0=4e00,4e40,4e80,4ec0,4f00,4f40,4f80,4fc0 +mma_ld: thrd=4,addr=65145344, fp16(size=16), stride=16 +thread0=5000,5020,5040,5060,5080,50a0,50c0,50e0 +mma_ld: thrd=5,addr=65145344, fp16(size=16), stride=16 +thread0=5100,5120,5140,5160,5180,51a0,51c0,51e0 +mma_ld: thrd=6,addr=65145344, fp16(size=16), stride=16 +thread0=5200,5220,5240,5260,5280,52a0,52c0,52e0 +mma_ld: thrd=7,addr=65145344, fp16(size=16), stride=16 +thread0=5300,5320,5340,5360,5380,53a0,53c0,53e0 +mma_ld: thrd=8,addr=65145344, fp16(size=16), stride=16 +thread0=5400,5410,5420,5430,5440,5450,5460,5470 +mma_ld: thrd=9,addr=65145344, fp16(size=16), stride=16 +thread0=5480,5490,54a0,54b0,54c0,54d0,54e0,54f0 +mma_ld: thrd=10,addr=65145344, fp16(size=16), stride=16 +thread0=5500,5510,5520,5530,5540,5550,5560,5570 +mma_ld: thrd=11,addr=65145344, fp16(size=16), stride=16 +thread0=5580,5590,55a0,55b0,55c0,55d0,55e0,55f0 +mma_ld: thrd=12,addr=65145344, fp16(size=16), stride=16 +thread0=5600,5610,5620,5630,5640,5650,5660,5670 +mma_ld: thrd=13,addr=65145344, fp16(size=16), stride=16 +thread0=5680,5690,56a0,56b0,56c0,56d0,56e0,56f0 +mma_ld: thrd=14,addr=65145344, fp16(size=16), stride=16 +thread0=5700,5710,5720,5730,5740,5750,5760,5770 +mma_ld: thrd=15,addr=65145344, fp16(size=16), stride=16 +thread0=5780,5790,57a0,57b0,57c0,57d0,57e0,57f0 +mma_ld: thrd=16,addr=65145344, fp16(size=16), stride=16 +thread0=5800,5808,5810,5818,5820,5828,5830,5838 +mma_ld: thrd=17,addr=65145344, fp16(size=16), stride=16 +thread0=5840,5848,5850,5858,5860,5868,5870,5878 +mma_ld: thrd=18,addr=65145344, fp16(size=16), stride=16 +thread0=5880,5888,5890,5898,58a0,58a8,58b0,58b8 +mma_ld: thrd=19,addr=65145344, fp16(size=16), stride=16 +thread0=58c0,58c8,58d0,58d8,58e0,58e8,58f0,58f8 +mma_ld: thrd=20,addr=65145344, fp16(size=16), stride=16 +thread0=5900,5908,5910,5918,5920,5928,5930,5938 +mma_ld: thrd=21,addr=65145344, fp16(size=16), stride=16 +thread0=5940,5948,5950,5958,5960,5968,5970,5978 +mma_ld: thrd=22,addr=65145344, fp16(size=16), stride=16 +thread0=5980,5988,5990,5998,59a0,59a8,59b0,59b8 +mma_ld: thrd=23,addr=65145344, fp16(size=16), stride=16 +thread0=59c0,59c8,59d0,59d8,59e0,59e8,59f0,59f8 +mma_ld: thrd=24,addr=65145344, fp16(size=16), stride=16 +thread0=5a00,5a08,5a10,5a18,5a20,5a28,5a30,5a38 +mma_ld: thrd=25,addr=65145344, fp16(size=16), stride=16 +thread0=5a40,5a48,5a50,5a58,5a60,5a68,5a70,5a78 +mma_ld: thrd=26,addr=65145344, fp16(size=16), stride=16 +thread0=5a80,5a88,5a90,5a98,5aa0,5aa8,5ab0,5ab8 +mma_ld: thrd=27,addr=65145344, fp16(size=16), stride=16 +thread0=5ac0,5ac8,5ad0,5ad8,5ae0,5ae8,5af0,5af8 +mma_ld: thrd=28,addr=65145344, fp16(size=16), stride=16 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data=5be8 +st:addr=3e20bfc data=5bf0 +st:addr=3e20bfe data=5bf8 diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core Binary files differindex cb53851..5b69818 100755 --- a/cuda-kernels/tensor_core +++ b/cuda-kernels/tensor_core diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index a65e8e1..d08a696 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -62,7 +62,7 @@ ifeq ($(GNUC_CPP0X),1) endif endif -OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o +OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o OPT += -DCUDART_VERSION=$(CUDART_VERSION) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 4721e8a..e38e499 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -64,6 +64,7 @@ * the above Disclaimer and U.S. Government End Users Notice. */ + #ifndef CUDA_MATH #define CUDA_MATH diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 62077e6..7552acf 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1311,7 +1311,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } - if((pI->get_opcode()!=MMA_OP)||((pI->get_opcode()==MMA_OP)&&(lane_id==0))){ + if(((pI->get_opcode()!=MMA_OP)&&(pI->get_opcode()!=MMA_LD_OP)&&(pI->get_opcode()!=MMA_ST_OP))||((pI->get_opcode()==MMA_OP||pI->get_opcode()==MMA_LD_OP||pI->get_opcode()==MMA_ST_OP)&&(lane_id==0))){ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; diff --git a/src/cuda-sim/half.hpp b/src/cuda-sim/half.hpp new file mode 100644 index 0000000..8f1a8eb --- /dev/null +++ b/src/cuda-sim/half.hpp @@ -0,0 +1,3067 @@ +// half - IEEE 754-based half-precision floating point library.
+//
+// Copyright (c) 2012-2017 Christian Rau <[email protected]>
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+// Version 1.12.0
+
+/// \file
+/// Main header file for half precision functionality.
+
+#ifndef HALF_HALF_HPP
+#define HALF_HALF_HPP
+
+/// Combined gcc version number.
+#define HALF_GNUC_VERSION (__GNUC__*100+__GNUC_MINOR__)
+
+//check C++11 language features
+#if defined(__clang__) //clang
+ #if __has_feature(cxx_static_assert) && !defined(HALF_ENABLE_CPP11_STATIC_ASSERT)
+ #define HALF_ENABLE_CPP11_STATIC_ASSERT 1
+ #endif
+ #if __has_feature(cxx_constexpr) && !defined(HALF_ENABLE_CPP11_CONSTEXPR)
+ #define HALF_ENABLE_CPP11_CONSTEXPR 1
+ #endif
+ #if __has_feature(cxx_noexcept) && !defined(HALF_ENABLE_CPP11_NOEXCEPT)
+ #define HALF_ENABLE_CPP11_NOEXCEPT 1
+ #endif
+ #if __has_feature(cxx_user_literals) && !defined(HALF_ENABLE_CPP11_USER_LITERALS)
+ #define HALF_ENABLE_CPP11_USER_LITERALS 1
+ #endif
+ #if (defined(__GXX_EXPERIMENTAL_CXX0X__) || __cplusplus >= 201103L) && !defined(HALF_ENABLE_CPP11_LONG_LONG)
+ #define HALF_ENABLE_CPP11_LONG_LONG 1
+ #endif
+/*#elif defined(__INTEL_COMPILER) //Intel C++
+ #if __INTEL_COMPILER >= 1100 && !defined(HALF_ENABLE_CPP11_STATIC_ASSERT) ????????
+ #define HALF_ENABLE_CPP11_STATIC_ASSERT 1
+ #endif
+ #if __INTEL_COMPILER >= 1300 && !defined(HALF_ENABLE_CPP11_CONSTEXPR) ????????
+ #define HALF_ENABLE_CPP11_CONSTEXPR 1
+ #endif
+ #if __INTEL_COMPILER >= 1300 && !defined(HALF_ENABLE_CPP11_NOEXCEPT) ????????
+ #define HALF_ENABLE_CPP11_NOEXCEPT 1
+ #endif
+ #if __INTEL_COMPILER >= 1100 && !defined(HALF_ENABLE_CPP11_LONG_LONG) ????????
+ #define HALF_ENABLE_CPP11_LONG_LONG 1
+ #endif*/
+#elif defined(__GNUC__) //gcc
+ #if defined(__GXX_EXPERIMENTAL_CXX0X__) || __cplusplus >= 201103L
+ #if HALF_GNUC_VERSION >= 403 && !defined(HALF_ENABLE_CPP11_STATIC_ASSERT)
+ #define HALF_ENABLE_CPP11_STATIC_ASSERT 1
+ #endif
+ #if HALF_GNUC_VERSION >= 406 && !defined(HALF_ENABLE_CPP11_CONSTEXPR)
+ #define HALF_ENABLE_CPP11_CONSTEXPR 1
+ #endif
+ #if HALF_GNUC_VERSION >= 406 && !defined(HALF_ENABLE_CPP11_NOEXCEPT)
+ #define HALF_ENABLE_CPP11_NOEXCEPT 1
+ #endif
+ #if HALF_GNUC_VERSION >= 407 && !defined(HALF_ENABLE_CPP11_USER_LITERALS)
+ #define HALF_ENABLE_CPP11_USER_LITERALS 1
+ #endif
+ #if !defined(HALF_ENABLE_CPP11_LONG_LONG)
+ #define HALF_ENABLE_CPP11_LONG_LONG 1
+ #endif
+ #endif
+#elif defined(_MSC_VER) //Visual C++
+ #if _MSC_VER >= 1900 && !defined(HALF_ENABLE_CPP11_CONSTEXPR)
+ #define HALF_ENABLE_CPP11_CONSTEXPR 1
+ #endif
+ #if _MSC_VER >= 1900 && !defined(HALF_ENABLE_CPP11_NOEXCEPT)
+ #define HALF_ENABLE_CPP11_NOEXCEPT 1
+ #endif
+ #if _MSC_VER >= 1900 && !defined(HALF_ENABLE_CPP11_USER_LITERALS)
+ #define HALF_ENABLE_CPP11_USER_LITERALS 1
+ #endif
+ #if _MSC_VER >= 1600 && !defined(HALF_ENABLE_CPP11_STATIC_ASSERT)
+ #define HALF_ENABLE_CPP11_STATIC_ASSERT 1
+ #endif
+ #if _MSC_VER >= 1310 && !defined(HALF_ENABLE_CPP11_LONG_LONG)
+ #define HALF_ENABLE_CPP11_LONG_LONG 1
+ #endif
+ #define HALF_POP_WARNINGS 1
+ #pragma warning(push)
+ #pragma warning(disable : 4099 4127 4146) //struct vs class, constant in if, negative unsigned
+#endif
+
+//check C++11 library features
+#include <utility>
+#if defined(_LIBCPP_VERSION) //libc++
+ #if defined(__GXX_EXPERIMENTAL_CXX0X__) || __cplusplus >= 201103
+ #ifndef HALF_ENABLE_CPP11_TYPE_TRAITS
+ #define HALF_ENABLE_CPP11_TYPE_TRAITS 1
+ #endif
+ #ifndef HALF_ENABLE_CPP11_CSTDINT
+ #define HALF_ENABLE_CPP11_CSTDINT 1
+ #endif
+ #ifndef HALF_ENABLE_CPP11_CMATH
+ #define HALF_ENABLE_CPP11_CMATH 1
+ #endif
+ #ifndef HALF_ENABLE_CPP11_HASH
+ #define HALF_ENABLE_CPP11_HASH 1
+ #endif
+ #endif
+#elif defined(__GLIBCXX__) //libstdc++
+ #if defined(__GXX_EXPERIMENTAL_CXX0X__) || __cplusplus >= 201103
+ #ifdef __clang__
+ #if __GLIBCXX__ >= 20080606 && !defined(HALF_ENABLE_CPP11_TYPE_TRAITS)
+ #define HALF_ENABLE_CPP11_TYPE_TRAITS 1
+ #endif
+ #if __GLIBCXX__ >= 20080606 && !defined(HALF_ENABLE_CPP11_CSTDINT)
+ #define HALF_ENABLE_CPP11_CSTDINT 1
+ #endif
+ #if __GLIBCXX__ >= 20080606 && !defined(HALF_ENABLE_CPP11_CMATH)
+ #define HALF_ENABLE_CPP11_CMATH 1
+ #endif
+ #if __GLIBCXX__ >= 20080606 && !defined(HALF_ENABLE_CPP11_HASH)
+ #define HALF_ENABLE_CPP11_HASH 1
+ #endif
+ #else
+ #if HALF_GNUC_VERSION >= 403 && !defined(HALF_ENABLE_CPP11_CSTDINT)
+ #define HALF_ENABLE_CPP11_CSTDINT 1
+ #endif
+ #if HALF_GNUC_VERSION >= 403 && !defined(HALF_ENABLE_CPP11_CMATH)
+ #define HALF_ENABLE_CPP11_CMATH 1
+ #endif
+ #if HALF_GNUC_VERSION >= 403 && !defined(HALF_ENABLE_CPP11_HASH)
+ #define HALF_ENABLE_CPP11_HASH 1
+ #endif
+ #endif
+ #endif
+#elif defined(_CPPLIB_VER) //Dinkumware/Visual C++
+ #if _CPPLIB_VER >= 520
+ #ifndef HALF_ENABLE_CPP11_TYPE_TRAITS
+ #define HALF_ENABLE_CPP11_TYPE_TRAITS 1
+ #endif
+ #ifndef HALF_ENABLE_CPP11_CSTDINT
+ #define HALF_ENABLE_CPP11_CSTDINT 1
+ #endif
+ #ifndef HALF_ENABLE_CPP11_HASH
+ #define HALF_ENABLE_CPP11_HASH 1
+ #endif
+ #endif
+ #if _CPPLIB_VER >= 610
+ #ifndef HALF_ENABLE_CPP11_CMATH
+ #define HALF_ENABLE_CPP11_CMATH 1
+ #endif
+ #endif
+#endif
+#undef HALF_GNUC_VERSION
+
+//support constexpr
+#if HALF_ENABLE_CPP11_CONSTEXPR
+ #define HALF_CONSTEXPR constexpr
+ #define HALF_CONSTEXPR_CONST constexpr
+#else
+ #define HALF_CONSTEXPR
+ #define HALF_CONSTEXPR_CONST const
+#endif
+
+//support noexcept
+#if HALF_ENABLE_CPP11_NOEXCEPT
+ #define HALF_NOEXCEPT noexcept
+ #define HALF_NOTHROW noexcept
+#else
+ #define HALF_NOEXCEPT
+ #define HALF_NOTHROW throw()
+#endif
+
+#include <algorithm>
+#include <iostream>
+#include <limits>
+#include <climits>
+#include <cmath>
+#include <cstring>
+#if HALF_ENABLE_CPP11_TYPE_TRAITS
+ #include <type_traits>
+#endif
+#if HALF_ENABLE_CPP11_CSTDINT
+ #include <cstdint>
+#endif
+#if HALF_ENABLE_CPP11_HASH
+ #include <functional>
+#endif
+
+
+/// Default rounding mode.
+/// This specifies the rounding mode used for all conversions between [half](\ref half_float::half)s and `float`s as well as
+/// for the half_cast() if not specifying a rounding mode explicitly. It can be redefined (before including half.hpp) to one
+/// of the standard rounding modes using their respective constants or the equivalent values of `std::float_round_style`:
+///
+/// `std::float_round_style` | value | rounding
+/// ---------------------------------|-------|-------------------------
+/// `std::round_indeterminate` | -1 | fastest (default)
+/// `std::round_toward_zero` | 0 | toward zero
+/// `std::round_to_nearest` | 1 | to nearest
+/// `std::round_toward_infinity` | 2 | toward positive infinity
+/// `std::round_toward_neg_infinity` | 3 | toward negative infinity
+///
+/// By default this is set to `-1` (`std::round_indeterminate`), which uses truncation (round toward zero, but with overflows
+/// set to infinity) and is the fastest rounding mode possible. It can even be set to `std::numeric_limits<float>::round_style`
+/// to synchronize the rounding mode with that of the underlying single-precision implementation.
+#ifndef HALF_ROUND_STYLE
+ #define HALF_ROUND_STYLE -1 // = std::round_indeterminate
+#endif
+
+/// Tie-breaking behaviour for round to nearest.
+/// This specifies if ties in round to nearest should be resolved by rounding to the nearest even value. By default this is
+/// defined to `0` resulting in the faster but slightly more biased behaviour of rounding away from zero in half-way cases (and
+/// thus equal to the round() function), but can be redefined to `1` (before including half.hpp) if more IEEE-conformant
+/// behaviour is needed.
+#ifndef HALF_ROUND_TIES_TO_EVEN
+ #define HALF_ROUND_TIES_TO_EVEN 0 // ties away from zero
+#endif
+
+/// Value signaling overflow.
+/// In correspondence with `HUGE_VAL[F|L]` from `<cmath>` this symbol expands to a positive value signaling the overflow of an
+/// operation, in particular it just evaluates to positive infinity.
+#define HUGE_VALH std::numeric_limits<half_float::half>::infinity()
+
+/// Fast half-precision fma function.
+/// This symbol is only defined if the fma() function generally executes as fast as, or faster than, a separate
+/// half-precision multiplication followed by an addition. Due to the internal single-precision implementation of all
+/// arithmetic operations, this is in fact always the case.
+#define FP_FAST_FMAH 1
+
+#ifndef FP_ILOGB0
+ #define FP_ILOGB0 INT_MIN
+#endif
+#ifndef FP_ILOGBNAN
+ #define FP_ILOGBNAN INT_MAX
+#endif
+#ifndef FP_SUBNORMAL
+ #define FP_SUBNORMAL 0
+#endif
+#ifndef FP_ZERO
+ #define FP_ZERO 1
+#endif
+#ifndef FP_NAN
+ #define FP_NAN 2
+#endif
+#ifndef FP_INFINITE
+ #define FP_INFINITE 3
+#endif
+#ifndef FP_NORMAL
+ #define FP_NORMAL 4
+#endif
+
+
+/// Main namespace for half precision functionality.
+/// This namespace contains all the functionality provided by the library.
+namespace half_float
+{
+ class half;
+
+#if HALF_ENABLE_CPP11_USER_LITERALS
+ /// Library-defined half-precision literals.
+ /// Import this namespace to enable half-precision floating point literals:
+ /// ~~~~{.cpp}
+ /// using namespace half_float::literal;
+ /// half_float::half = 4.2_h;
+ /// ~~~~
+ namespace literal
+ {
+ half operator"" _h(long double);
+ }
+#endif
+
+ /// \internal
+ /// \brief Implementation details.
+ namespace detail
+ {
+ #if HALF_ENABLE_CPP11_TYPE_TRAITS
+ /// Conditional type.
+ template<bool B,typename T,typename F> struct conditional : std::conditional<B,T,F> {};
+
+ /// Helper for tag dispatching.
+ template<bool B> struct bool_type : std::integral_constant<bool,B> {};
+ using std::true_type;
+ using std::false_type;
+
+ /// Type traits for floating point types.
+ template<typename T> struct is_float : std::is_floating_point<T> {};
+ #else
+ /// Conditional type.
+ template<bool,typename T,typename> struct conditional { typedef T type; };
+ template<typename T,typename F> struct conditional<false,T,F> { typedef F type; };
+
+ /// Helper for tag dispatching.
+ template<bool> struct bool_type {};
+ typedef bool_type<true> true_type;
+ typedef bool_type<false> false_type;
+
+ /// Type traits for floating point types.
+ template<typename> struct is_float : false_type {};
+ template<typename T> struct is_float<const T> : is_float<T> {};
+ template<typename T> struct is_float<volatile T> : is_float<T> {};
+ template<typename T> struct is_float<const volatile T> : is_float<T> {};
+ template<> struct is_float<float> : true_type {};
+ template<> struct is_float<double> : true_type {};
+ template<> struct is_float<long double> : true_type {};
+ #endif
+
+ /// Type traits for floating point bits.
+ template<typename T> struct bits { typedef unsigned char type; };
+ template<typename T> struct bits<const T> : bits<T> {};
+ template<typename T> struct bits<volatile T> : bits<T> {};
+ template<typename T> struct bits<const volatile T> : bits<T> {};
+
+ #if HALF_ENABLE_CPP11_CSTDINT
+ /// Unsigned integer of (at least) 16 bits width.
+ typedef std::uint_least16_t uint16;
+
+ /// Unsigned integer of (at least) 32 bits width.
+ template<> struct bits<float> { typedef std::uint_least32_t type; };
+
+ /// Unsigned integer of (at least) 64 bits width.
+ template<> struct bits<double> { typedef std::uint_least64_t type; };
+ #else
+ /// Unsigned integer of (at least) 16 bits width.
+ typedef unsigned short uint16;
+
+ /// Unsigned integer of (at least) 32 bits width.
+ template<> struct bits<float> : conditional<std::numeric_limits<unsigned int>::digits>=32,unsigned int,unsigned long> {};
+
+ #if HALF_ENABLE_CPP11_LONG_LONG
+ /// Unsigned integer of (at least) 64 bits width.
+ template<> struct bits<double> : conditional<std::numeric_limits<unsigned long>::digits>=64,unsigned long,unsigned long long> {};
+ #else
+ /// Unsigned integer of (at least) 64 bits width.
+ template<> struct bits<double> { typedef unsigned long type; };
+ #endif
+ #endif
+
+ /// Tag type for binary construction.
+ struct binary_t {};
+
+ /// Tag for binary construction.
+ HALF_CONSTEXPR_CONST binary_t binary = binary_t();
+
+ /// Temporary half-precision expression.
+ /// This class represents a half-precision expression which just stores a single-precision value internally.
+ struct expr
+ {
+ /// Conversion constructor.
+ /// \param f single-precision value to convert
+ explicit HALF_CONSTEXPR expr(float f) HALF_NOEXCEPT : value_(f) {}
+
+ /// Conversion to single-precision.
+ /// \return single precision value representing expression value
+ HALF_CONSTEXPR operator float() const HALF_NOEXCEPT { return value_; }
+
+ private:
+ /// Internal expression value stored in single-precision.
+ float value_;
+ };
+
+ /// SFINAE helper for generic half-precision functions.
+ /// This class template has to be specialized for each valid combination of argument types to provide a corresponding
+ /// `type` member equivalent to \a T.
+ /// \tparam T type to return
+ template<typename T,typename,typename=void,typename=void> struct enable {};
+ template<typename T> struct enable<T,half,void,void> { typedef T type; };
+ template<typename T> struct enable<T,expr,void,void> { typedef T type; };
+ template<typename T> struct enable<T,half,half,void> { typedef T type; };
+ template<typename T> struct enable<T,half,expr,void> { typedef T type; };
+ template<typename T> struct enable<T,expr,half,void> { typedef T type; };
+ template<typename T> struct enable<T,expr,expr,void> { typedef T type; };
+ template<typename T> struct enable<T,half,half,half> { typedef T type; };
+ template<typename T> struct enable<T,half,half,expr> { typedef T type; };
+ template<typename T> struct enable<T,half,expr,half> { typedef T type; };
+ template<typename T> struct enable<T,half,expr,expr> { typedef T type; };
+ template<typename T> struct enable<T,expr,half,half> { typedef T type; };
+ template<typename T> struct enable<T,expr,half,expr> { typedef T type; };
+ template<typename T> struct enable<T,expr,expr,half> { typedef T type; };
+ template<typename T> struct enable<T,expr,expr,expr> { typedef T type; };
+
+ /// Return type for specialized generic 2-argument half-precision functions.
+ /// This class template has to be specialized for each valid combination of argument types to provide a corresponding
+ /// `type` member denoting the appropriate return type.
+ /// \tparam T first argument type
+ /// \tparam U first argument type
+ template<typename T,typename U> struct result : enable<expr,T,U> {};
+ template<> struct result<half,half> { typedef half type; };
+
+ /// \name Classification helpers
+ /// \{
+
+ /// Check for infinity.
+ /// \tparam T argument type (builtin floating point type)
+ /// \param arg value to query
+ /// \retval true if infinity
+ /// \retval false else
+ template<typename T> bool builtin_isinf(T arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return std::isinf(arg);
+ #elif defined(_MSC_VER)
+ return !::_finite(static_cast<double>(arg)) && !::_isnan(static_cast<double>(arg));
+ #else
+ return arg == std::numeric_limits<T>::infinity() || arg == -std::numeric_limits<T>::infinity();
+ #endif
+ }
+
+ /// Check for NaN.
+ /// \tparam T argument type (builtin floating point type)
+ /// \param arg value to query
+ /// \retval true if not a number
+ /// \retval false else
+ template<typename T> bool builtin_isnan(T arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return std::isnan(arg);
+ #elif defined(_MSC_VER)
+ return ::_isnan(static_cast<double>(arg)) != 0;
+ #else
+ return arg != arg;
+ #endif
+ }
+
+ /// Check sign.
+ /// \tparam T argument type (builtin floating point type)
+ /// \param arg value to query
+ /// \retval true if signbit set
+ /// \retval false else
+ template<typename T> bool builtin_signbit(T arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return std::signbit(arg);
+ #else
+ return arg < T() || (arg == T() && T(1)/arg < T());
+ #endif
+ }
+
+ /// \}
+ /// \name Conversion
+ /// \{
+
+ /// Convert IEEE single-precision to half-precision.
+ /// Credit for this goes to [Jeroen van der Zijp](ftp://ftp.fox-toolkit.org/pub/fasthalffloatconversion.pdf).
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \param value single-precision value
+ /// \return binary representation of half-precision value
+ template<std::float_round_style R> uint16 float2half_impl(float value, true_type)
+ {
+ typedef bits<float>::type uint32;
+ uint32 bits;// = *reinterpret_cast<uint32*>(&value); //violating strict aliasing!
+ std::memcpy(&bits, &value, sizeof(float));
+/* uint16 hbits = (bits>>16) & 0x8000;
+ bits &= 0x7FFFFFFF;
+ int exp = bits >> 23;
+ if(exp == 255)
+ return hbits | 0x7C00 | (0x3FF&-static_cast<unsigned>((bits&0x7FFFFF)!=0));
+ if(exp > 142)
+ {
+ if(R == std::round_toward_infinity)
+ return hbits | 0x7C00 - (hbits>>15);
+ if(R == std::round_toward_neg_infinity)
+ return hbits | 0x7BFF + (hbits>>15);
+ return hbits | 0x7BFF + (R!=std::round_toward_zero);
+ }
+ int g, s;
+ if(exp > 112)
+ {
+ g = (bits>>12) & 1;
+ s = (bits&0xFFF) != 0;
+ hbits |= ((exp-112)<<10) | ((bits>>13)&0x3FF);
+ }
+ else if(exp > 101)
+ {
+ int i = 125 - exp;
+ bits = (bits&0x7FFFFF) | 0x800000;
+ g = (bits>>i) & 1;
+ s = (bits&((1L<<i)-1)) != 0;
+ hbits |= bits >> (i+1);
+ }
+ else
+ {
+ g = 0;
+ s = bits != 0;
+ }
+ if(R == std::round_to_nearest)
+ #if HALF_ROUND_TIES_TO_EVEN
+ hbits += g & (s|hbits);
+ #else
+ hbits += g;
+ #endif
+ else if(R == std::round_toward_infinity)
+ hbits += ~(hbits>>15) & (s|g);
+ else if(R == std::round_toward_neg_infinity)
+ hbits += (hbits>>15) & (g|s);
+*/ static const uint16 base_table[512] = {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100,
+ 0x0200, 0x0400, 0x0800, 0x0C00, 0x1000, 0x1400, 0x1800, 0x1C00, 0x2000, 0x2400, 0x2800, 0x2C00, 0x3000, 0x3400, 0x3800, 0x3C00,
+ 0x4000, 0x4400, 0x4800, 0x4C00, 0x5000, 0x5400, 0x5800, 0x5C00, 0x6000, 0x6400, 0x6800, 0x6C00, 0x7000, 0x7400, 0x7800, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00, 0x7C00,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8002, 0x8004, 0x8008, 0x8010, 0x8020, 0x8040, 0x8080, 0x8100,
+ 0x8200, 0x8400, 0x8800, 0x8C00, 0x9000, 0x9400, 0x9800, 0x9C00, 0xA000, 0xA400, 0xA800, 0xAC00, 0xB000, 0xB400, 0xB800, 0xBC00,
+ 0xC000, 0xC400, 0xC800, 0xCC00, 0xD000, 0xD400, 0xD800, 0xDC00, 0xE000, 0xE400, 0xE800, 0xEC00, 0xF000, 0xF400, 0xF800, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00,
+ 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00, 0xFC00 };
+ static const unsigned char shift_table[512] = {
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 13,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 13 };
+ uint16 hbits = base_table[bits>>23] + static_cast<uint16>((bits&0x7FFFFF)>>shift_table[bits>>23]);
+ if(R == std::round_to_nearest)
+ hbits += (((bits&0x7FFFFF)>>(shift_table[bits>>23]-1))|(((bits>>23)&0xFF)==102)) & ((hbits&0x7C00)!=0x7C00)
+ #if HALF_ROUND_TIES_TO_EVEN
+ & (((((static_cast<uint32>(1)<<(shift_table[bits>>23]-1))-1)&bits)!=0)|hbits)
+ #endif
+ ;
+ else if(R == std::round_toward_zero)
+ hbits -= ((hbits&0x7FFF)==0x7C00) & ~shift_table[bits>>23];
+ else if(R == std::round_toward_infinity)
+ hbits += ((((bits&0x7FFFFF&((static_cast<uint32>(1)<<(shift_table[bits>>23]))-1))!=0)|(((bits>>23)<=102)&
+ ((bits>>23)!=0)))&(hbits<0x7C00)) - ((hbits==0xFC00)&((bits>>23)!=511));
+ else if(R == std::round_toward_neg_infinity)
+ hbits += ((((bits&0x7FFFFF&((static_cast<uint32>(1)<<(shift_table[bits>>23]))-1))!=0)|(((bits>>23)<=358)&
+ ((bits>>23)!=256)))&(hbits<0xFC00)&(hbits>>15)) - ((hbits==0x7C00)&((bits>>23)!=255));
+ return hbits;
+ }
+
+ /// Convert IEEE double-precision to half-precision.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \param value double-precision value
+ /// \return binary representation of half-precision value
+ template<std::float_round_style R> uint16 float2half_impl(double value, true_type)
+ {
+ typedef bits<float>::type uint32;
+ typedef bits<double>::type uint64;
+ uint64 bits;// = *reinterpret_cast<uint64*>(&value); //violating strict aliasing!
+ std::memcpy(&bits, &value, sizeof(double));
+ uint32 hi = bits >> 32, lo = bits & 0xFFFFFFFF;
+ uint16 hbits = (hi>>16) & 0x8000;
+ hi &= 0x7FFFFFFF;
+ int exp = hi >> 20;
+ if(exp == 2047)
+ return hbits | 0x7C00 | (0x3FF&-static_cast<unsigned>((bits&0xFFFFFFFFFFFFF)!=0));
+ if(exp > 1038)
+ {
+ if(R == std::round_toward_infinity)
+ return hbits | 0x7C00 - (hbits>>15);
+ if(R == std::round_toward_neg_infinity)
+ return hbits | 0x7BFF + (hbits>>15);
+ return hbits | 0x7BFF + (R!=std::round_toward_zero);
+ }
+ int g, s = lo != 0;
+ if(exp > 1008)
+ {
+ g = (hi>>9) & 1;
+ s |= (hi&0x1FF) != 0;
+ hbits |= ((exp-1008)<<10) | ((hi>>10)&0x3FF);
+ }
+ else if(exp > 997)
+ {
+ int i = 1018 - exp;
+ hi = (hi&0xFFFFF) | 0x100000;
+ g = (hi>>i) & 1;
+ s |= (hi&((1L<<i)-1)) != 0;
+ hbits |= hi >> (i+1);
+ }
+ else
+ {
+ g = 0;
+ s |= hi != 0;
+ }
+ if(R == std::round_to_nearest)
+ #if HALF_ROUND_TIES_TO_EVEN
+ hbits += g & (s|hbits);
+ #else
+ hbits += g;
+ #endif
+ else if(R == std::round_toward_infinity)
+ hbits += ~(hbits>>15) & (s|g);
+ else if(R == std::round_toward_neg_infinity)
+ hbits += (hbits>>15) & (g|s);
+ return hbits;
+ }
+
+ /// Convert non-IEEE floating point to half-precision.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam T source type (builtin floating point type)
+ /// \param value floating point value
+ /// \return binary representation of half-precision value
+ template<std::float_round_style R,typename T> uint16 float2half_impl(T value, ...)
+ {
+ uint16 hbits = static_cast<unsigned>(builtin_signbit(value)) << 15;
+ if(value == T())
+ return hbits;
+ if(builtin_isnan(value))
+ return hbits | 0x7FFF;
+ if(builtin_isinf(value))
+ return hbits | 0x7C00;
+ int exp;
+ std::frexp(value, &exp);
+ if(exp > 16)
+ {
+ if(R == std::round_toward_infinity)
+ return hbits | 0x7C00 - (hbits>>15);
+ else if(R == std::round_toward_neg_infinity)
+ return hbits | 0x7BFF + (hbits>>15);
+ return hbits | 0x7BFF + (R!=std::round_toward_zero);
+ }
+ if(exp < -13)
+ value = std::ldexp(value, 24);
+ else
+ {
+ value = std::ldexp(value, 11-exp);
+ hbits |= ((exp+13)<<10);
+ }
+ T ival, frac = std::modf(value, &ival);
+ hbits += static_cast<uint16>(std::abs(static_cast<int>(ival)));
+ if(R == std::round_to_nearest)
+ {
+ frac = std::abs(frac);
+ #if HALF_ROUND_TIES_TO_EVEN
+ hbits += (frac>T(0.5)) | ((frac==T(0.5))&hbits);
+ #else
+ hbits += frac >= T(0.5);
+ #endif
+ }
+ else if(R == std::round_toward_infinity)
+ hbits += frac > T();
+ else if(R == std::round_toward_neg_infinity)
+ hbits += frac < T();
+ return hbits;
+ }
+
+ /// Convert floating point to half-precision.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam T source type (builtin floating point type)
+ /// \param value floating point value
+ /// \return binary representation of half-precision value
+ template<std::float_round_style R,typename T> uint16 float2half(T value)
+ {
+ return float2half_impl<R>(value, bool_type<std::numeric_limits<T>::is_iec559&&sizeof(typename bits<T>::type)==sizeof(T)>());
+ }
+
+ /// Convert integer to half-precision floating point.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam S `true` if value negative, `false` else
+ /// \tparam T type to convert (builtin integer type)
+ /// \param value non-negative integral value
+ /// \return binary representation of half-precision value
+ template<std::float_round_style R,bool S,typename T> uint16 int2half_impl(T value)
+ {
+ #if HALF_ENABLE_CPP11_STATIC_ASSERT && HALF_ENABLE_CPP11_TYPE_TRAITS
+ static_assert(std::is_integral<T>::value, "int to half conversion only supports builtin integer types");
+ #endif
+ if(S)
+ value = -value;
+ uint16 bits = S << 15;
+ if(value > 0xFFFF)
+ {
+ if(R == std::round_toward_infinity)
+ bits |= 0x7C00 - S;
+ else if(R == std::round_toward_neg_infinity)
+ bits |= 0x7BFF + S;
+ else
+ bits |= 0x7BFF + (R!=std::round_toward_zero);
+ }
+ else if(value)
+ {
+ unsigned int m = value, exp = 24;
+ for(; m<0x400; m<<=1,--exp) ;
+ for(; m>0x7FF; m>>=1,++exp) ;
+ bits |= (exp<<10) + m;
+ if(exp > 24)
+ {
+ if(R == std::round_to_nearest)
+ bits += (value>>(exp-25)) & 1
+ #if HALF_ROUND_TIES_TO_EVEN
+ & (((((1<<(exp-25))-1)&value)!=0)|bits)
+ #endif
+ ;
+ else if(R == std::round_toward_infinity)
+ bits += ((value&((1<<(exp-24))-1))!=0) & !S;
+ else if(R == std::round_toward_neg_infinity)
+ bits += ((value&((1<<(exp-24))-1))!=0) & S;
+ }
+ }
+ return bits;
+ }
+
+ /// Convert integer to half-precision floating point.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam T type to convert (builtin integer type)
+ /// \param value integral value
+ /// \return binary representation of half-precision value
+ template<std::float_round_style R,typename T> uint16 int2half(T value)
+ {
+ return (value<0) ? int2half_impl<R,true>(value) : int2half_impl<R,false>(value);
+ }
+
+ /// Convert half-precision to IEEE single-precision.
+ /// Credit for this goes to [Jeroen van der Zijp](ftp://ftp.fox-toolkit.org/pub/fasthalffloatconversion.pdf).
+ /// \param value binary representation of half-precision value
+ /// \return single-precision value
+ inline float half2float_impl(uint16 value, float, true_type)
+ {
+ typedef bits<float>::type uint32;
+/* uint32 bits = static_cast<uint32>(value&0x8000) << 16;
+ int abs = value & 0x7FFF;
+ if(abs)
+ {
+ bits |= 0x38000000 << static_cast<unsigned>(abs>=0x7C00);
+ for(; abs<0x400; abs<<=1,bits-=0x800000) ;
+ bits += static_cast<uint32>(abs) << 13;
+ }
+*/ static const uint32 mantissa_table[2048] = {
+ 0x00000000, 0x33800000, 0x34000000, 0x34400000, 0x34800000, 0x34A00000, 0x34C00000, 0x34E00000, 0x35000000, 0x35100000, 0x35200000, 0x35300000, 0x35400000, 0x35500000, 0x35600000, 0x35700000,
+ 0x35800000, 0x35880000, 0x35900000, 0x35980000, 0x35A00000, 0x35A80000, 0x35B00000, 0x35B80000, 0x35C00000, 0x35C80000, 0x35D00000, 0x35D80000, 0x35E00000, 0x35E80000, 0x35F00000, 0x35F80000,
+ 0x36000000, 0x36040000, 0x36080000, 0x360C0000, 0x36100000, 0x36140000, 0x36180000, 0x361C0000, 0x36200000, 0x36240000, 0x36280000, 0x362C0000, 0x36300000, 0x36340000, 0x36380000, 0x363C0000,
+ 0x36400000, 0x36440000, 0x36480000, 0x364C0000, 0x36500000, 0x36540000, 0x36580000, 0x365C0000, 0x36600000, 0x36640000, 0x36680000, 0x366C0000, 0x36700000, 0x36740000, 0x36780000, 0x367C0000,
+ 0x36800000, 0x36820000, 0x36840000, 0x36860000, 0x36880000, 0x368A0000, 0x368C0000, 0x368E0000, 0x36900000, 0x36920000, 0x36940000, 0x36960000, 0x36980000, 0x369A0000, 0x369C0000, 0x369E0000,
+ 0x36A00000, 0x36A20000, 0x36A40000, 0x36A60000, 0x36A80000, 0x36AA0000, 0x36AC0000, 0x36AE0000, 0x36B00000, 0x36B20000, 0x36B40000, 0x36B60000, 0x36B80000, 0x36BA0000, 0x36BC0000, 0x36BE0000,
+ 0x36C00000, 0x36C20000, 0x36C40000, 0x36C60000, 0x36C80000, 0x36CA0000, 0x36CC0000, 0x36CE0000, 0x36D00000, 0x36D20000, 0x36D40000, 0x36D60000, 0x36D80000, 0x36DA0000, 0x36DC0000, 0x36DE0000,
+ 0x36E00000, 0x36E20000, 0x36E40000, 0x36E60000, 0x36E80000, 0x36EA0000, 0x36EC0000, 0x36EE0000, 0x36F00000, 0x36F20000, 0x36F40000, 0x36F60000, 0x36F80000, 0x36FA0000, 0x36FC0000, 0x36FE0000,
+ 0x37000000, 0x37010000, 0x37020000, 0x37030000, 0x37040000, 0x37050000, 0x37060000, 0x37070000, 0x37080000, 0x37090000, 0x370A0000, 0x370B0000, 0x370C0000, 0x370D0000, 0x370E0000, 0x370F0000,
+ 0x37100000, 0x37110000, 0x37120000, 0x37130000, 0x37140000, 0x37150000, 0x37160000, 0x37170000, 0x37180000, 0x37190000, 0x371A0000, 0x371B0000, 0x371C0000, 0x371D0000, 0x371E0000, 0x371F0000,
+ 0x37200000, 0x37210000, 0x37220000, 0x37230000, 0x37240000, 0x37250000, 0x37260000, 0x37270000, 0x37280000, 0x37290000, 0x372A0000, 0x372B0000, 0x372C0000, 0x372D0000, 0x372E0000, 0x372F0000,
+ 0x37300000, 0x37310000, 0x37320000, 0x37330000, 0x37340000, 0x37350000, 0x37360000, 0x37370000, 0x37380000, 0x37390000, 0x373A0000, 0x373B0000, 0x373C0000, 0x373D0000, 0x373E0000, 0x373F0000,
+ 0x37400000, 0x37410000, 0x37420000, 0x37430000, 0x37440000, 0x37450000, 0x37460000, 0x37470000, 0x37480000, 0x37490000, 0x374A0000, 0x374B0000, 0x374C0000, 0x374D0000, 0x374E0000, 0x374F0000,
+ 0x37500000, 0x37510000, 0x37520000, 0x37530000, 0x37540000, 0x37550000, 0x37560000, 0x37570000, 0x37580000, 0x37590000, 0x375A0000, 0x375B0000, 0x375C0000, 0x375D0000, 0x375E0000, 0x375F0000,
+ 0x37600000, 0x37610000, 0x37620000, 0x37630000, 0x37640000, 0x37650000, 0x37660000, 0x37670000, 0x37680000, 0x37690000, 0x376A0000, 0x376B0000, 0x376C0000, 0x376D0000, 0x376E0000, 0x376F0000,
+ 0x37700000, 0x37710000, 0x37720000, 0x37730000, 0x37740000, 0x37750000, 0x37760000, 0x37770000, 0x37780000, 0x37790000, 0x377A0000, 0x377B0000, 0x377C0000, 0x377D0000, 0x377E0000, 0x377F0000,
+ 0x37800000, 0x37808000, 0x37810000, 0x37818000, 0x37820000, 0x37828000, 0x37830000, 0x37838000, 0x37840000, 0x37848000, 0x37850000, 0x37858000, 0x37860000, 0x37868000, 0x37870000, 0x37878000,
+ 0x37880000, 0x37888000, 0x37890000, 0x37898000, 0x378A0000, 0x378A8000, 0x378B0000, 0x378B8000, 0x378C0000, 0x378C8000, 0x378D0000, 0x378D8000, 0x378E0000, 0x378E8000, 0x378F0000, 0x378F8000,
+ 0x37900000, 0x37908000, 0x37910000, 0x37918000, 0x37920000, 0x37928000, 0x37930000, 0x37938000, 0x37940000, 0x37948000, 0x37950000, 0x37958000, 0x37960000, 0x37968000, 0x37970000, 0x37978000,
+ 0x37980000, 0x37988000, 0x37990000, 0x37998000, 0x379A0000, 0x379A8000, 0x379B0000, 0x379B8000, 0x379C0000, 0x379C8000, 0x379D0000, 0x379D8000, 0x379E0000, 0x379E8000, 0x379F0000, 0x379F8000,
+ 0x37A00000, 0x37A08000, 0x37A10000, 0x37A18000, 0x37A20000, 0x37A28000, 0x37A30000, 0x37A38000, 0x37A40000, 0x37A48000, 0x37A50000, 0x37A58000, 0x37A60000, 0x37A68000, 0x37A70000, 0x37A78000,
+ 0x37A80000, 0x37A88000, 0x37A90000, 0x37A98000, 0x37AA0000, 0x37AA8000, 0x37AB0000, 0x37AB8000, 0x37AC0000, 0x37AC8000, 0x37AD0000, 0x37AD8000, 0x37AE0000, 0x37AE8000, 0x37AF0000, 0x37AF8000,
+ 0x37B00000, 0x37B08000, 0x37B10000, 0x37B18000, 0x37B20000, 0x37B28000, 0x37B30000, 0x37B38000, 0x37B40000, 0x37B48000, 0x37B50000, 0x37B58000, 0x37B60000, 0x37B68000, 0x37B70000, 0x37B78000,
+ 0x37B80000, 0x37B88000, 0x37B90000, 0x37B98000, 0x37BA0000, 0x37BA8000, 0x37BB0000, 0x37BB8000, 0x37BC0000, 0x37BC8000, 0x37BD0000, 0x37BD8000, 0x37BE0000, 0x37BE8000, 0x37BF0000, 0x37BF8000,
+ 0x37C00000, 0x37C08000, 0x37C10000, 0x37C18000, 0x37C20000, 0x37C28000, 0x37C30000, 0x37C38000, 0x37C40000, 0x37C48000, 0x37C50000, 0x37C58000, 0x37C60000, 0x37C68000, 0x37C70000, 0x37C78000,
+ 0x37C80000, 0x37C88000, 0x37C90000, 0x37C98000, 0x37CA0000, 0x37CA8000, 0x37CB0000, 0x37CB8000, 0x37CC0000, 0x37CC8000, 0x37CD0000, 0x37CD8000, 0x37CE0000, 0x37CE8000, 0x37CF0000, 0x37CF8000,
+ 0x37D00000, 0x37D08000, 0x37D10000, 0x37D18000, 0x37D20000, 0x37D28000, 0x37D30000, 0x37D38000, 0x37D40000, 0x37D48000, 0x37D50000, 0x37D58000, 0x37D60000, 0x37D68000, 0x37D70000, 0x37D78000,
+ 0x37D80000, 0x37D88000, 0x37D90000, 0x37D98000, 0x37DA0000, 0x37DA8000, 0x37DB0000, 0x37DB8000, 0x37DC0000, 0x37DC8000, 0x37DD0000, 0x37DD8000, 0x37DE0000, 0x37DE8000, 0x37DF0000, 0x37DF8000,
+ 0x37E00000, 0x37E08000, 0x37E10000, 0x37E18000, 0x37E20000, 0x37E28000, 0x37E30000, 0x37E38000, 0x37E40000, 0x37E48000, 0x37E50000, 0x37E58000, 0x37E60000, 0x37E68000, 0x37E70000, 0x37E78000,
+ 0x37E80000, 0x37E88000, 0x37E90000, 0x37E98000, 0x37EA0000, 0x37EA8000, 0x37EB0000, 0x37EB8000, 0x37EC0000, 0x37EC8000, 0x37ED0000, 0x37ED8000, 0x37EE0000, 0x37EE8000, 0x37EF0000, 0x37EF8000,
+ 0x37F00000, 0x37F08000, 0x37F10000, 0x37F18000, 0x37F20000, 0x37F28000, 0x37F30000, 0x37F38000, 0x37F40000, 0x37F48000, 0x37F50000, 0x37F58000, 0x37F60000, 0x37F68000, 0x37F70000, 0x37F78000,
+ 0x37F80000, 0x37F88000, 0x37F90000, 0x37F98000, 0x37FA0000, 0x37FA8000, 0x37FB0000, 0x37FB8000, 0x37FC0000, 0x37FC8000, 0x37FD0000, 0x37FD8000, 0x37FE0000, 0x37FE8000, 0x37FF0000, 0x37FF8000,
+ 0x38000000, 0x38004000, 0x38008000, 0x3800C000, 0x38010000, 0x38014000, 0x38018000, 0x3801C000, 0x38020000, 0x38024000, 0x38028000, 0x3802C000, 0x38030000, 0x38034000, 0x38038000, 0x3803C000,
+ 0x38040000, 0x38044000, 0x38048000, 0x3804C000, 0x38050000, 0x38054000, 0x38058000, 0x3805C000, 0x38060000, 0x38064000, 0x38068000, 0x3806C000, 0x38070000, 0x38074000, 0x38078000, 0x3807C000,
+ 0x38080000, 0x38084000, 0x38088000, 0x3808C000, 0x38090000, 0x38094000, 0x38098000, 0x3809C000, 0x380A0000, 0x380A4000, 0x380A8000, 0x380AC000, 0x380B0000, 0x380B4000, 0x380B8000, 0x380BC000,
+ 0x380C0000, 0x380C4000, 0x380C8000, 0x380CC000, 0x380D0000, 0x380D4000, 0x380D8000, 0x380DC000, 0x380E0000, 0x380E4000, 0x380E8000, 0x380EC000, 0x380F0000, 0x380F4000, 0x380F8000, 0x380FC000,
+ 0x38100000, 0x38104000, 0x38108000, 0x3810C000, 0x38110000, 0x38114000, 0x38118000, 0x3811C000, 0x38120000, 0x38124000, 0x38128000, 0x3812C000, 0x38130000, 0x38134000, 0x38138000, 0x3813C000,
+ 0x38140000, 0x38144000, 0x38148000, 0x3814C000, 0x38150000, 0x38154000, 0x38158000, 0x3815C000, 0x38160000, 0x38164000, 0x38168000, 0x3816C000, 0x38170000, 0x38174000, 0x38178000, 0x3817C000,
+ 0x38180000, 0x38184000, 0x38188000, 0x3818C000, 0x38190000, 0x38194000, 0x38198000, 0x3819C000, 0x381A0000, 0x381A4000, 0x381A8000, 0x381AC000, 0x381B0000, 0x381B4000, 0x381B8000, 0x381BC000,
+ 0x381C0000, 0x381C4000, 0x381C8000, 0x381CC000, 0x381D0000, 0x381D4000, 0x381D8000, 0x381DC000, 0x381E0000, 0x381E4000, 0x381E8000, 0x381EC000, 0x381F0000, 0x381F4000, 0x381F8000, 0x381FC000,
+ 0x38200000, 0x38204000, 0x38208000, 0x3820C000, 0x38210000, 0x38214000, 0x38218000, 0x3821C000, 0x38220000, 0x38224000, 0x38228000, 0x3822C000, 0x38230000, 0x38234000, 0x38238000, 0x3823C000,
+ 0x38240000, 0x38244000, 0x38248000, 0x3824C000, 0x38250000, 0x38254000, 0x38258000, 0x3825C000, 0x38260000, 0x38264000, 0x38268000, 0x3826C000, 0x38270000, 0x38274000, 0x38278000, 0x3827C000,
+ 0x38280000, 0x38284000, 0x38288000, 0x3828C000, 0x38290000, 0x38294000, 0x38298000, 0x3829C000, 0x382A0000, 0x382A4000, 0x382A8000, 0x382AC000, 0x382B0000, 0x382B4000, 0x382B8000, 0x382BC000,
+ 0x382C0000, 0x382C4000, 0x382C8000, 0x382CC000, 0x382D0000, 0x382D4000, 0x382D8000, 0x382DC000, 0x382E0000, 0x382E4000, 0x382E8000, 0x382EC000, 0x382F0000, 0x382F4000, 0x382F8000, 0x382FC000,
+ 0x38300000, 0x38304000, 0x38308000, 0x3830C000, 0x38310000, 0x38314000, 0x38318000, 0x3831C000, 0x38320000, 0x38324000, 0x38328000, 0x3832C000, 0x38330000, 0x38334000, 0x38338000, 0x3833C000,
+ 0x38340000, 0x38344000, 0x38348000, 0x3834C000, 0x38350000, 0x38354000, 0x38358000, 0x3835C000, 0x38360000, 0x38364000, 0x38368000, 0x3836C000, 0x38370000, 0x38374000, 0x38378000, 0x3837C000,
+ 0x38380000, 0x38384000, 0x38388000, 0x3838C000, 0x38390000, 0x38394000, 0x38398000, 0x3839C000, 0x383A0000, 0x383A4000, 0x383A8000, 0x383AC000, 0x383B0000, 0x383B4000, 0x383B8000, 0x383BC000,
+ 0x383C0000, 0x383C4000, 0x383C8000, 0x383CC000, 0x383D0000, 0x383D4000, 0x383D8000, 0x383DC000, 0x383E0000, 0x383E4000, 0x383E8000, 0x383EC000, 0x383F0000, 0x383F4000, 0x383F8000, 0x383FC000,
+ 0x38400000, 0x38404000, 0x38408000, 0x3840C000, 0x38410000, 0x38414000, 0x38418000, 0x3841C000, 0x38420000, 0x38424000, 0x38428000, 0x3842C000, 0x38430000, 0x38434000, 0x38438000, 0x3843C000,
+ 0x38440000, 0x38444000, 0x38448000, 0x3844C000, 0x38450000, 0x38454000, 0x38458000, 0x3845C000, 0x38460000, 0x38464000, 0x38468000, 0x3846C000, 0x38470000, 0x38474000, 0x38478000, 0x3847C000,
+ 0x38480000, 0x38484000, 0x38488000, 0x3848C000, 0x38490000, 0x38494000, 0x38498000, 0x3849C000, 0x384A0000, 0x384A4000, 0x384A8000, 0x384AC000, 0x384B0000, 0x384B4000, 0x384B8000, 0x384BC000,
+ 0x384C0000, 0x384C4000, 0x384C8000, 0x384CC000, 0x384D0000, 0x384D4000, 0x384D8000, 0x384DC000, 0x384E0000, 0x384E4000, 0x384E8000, 0x384EC000, 0x384F0000, 0x384F4000, 0x384F8000, 0x384FC000,
+ 0x38500000, 0x38504000, 0x38508000, 0x3850C000, 0x38510000, 0x38514000, 0x38518000, 0x3851C000, 0x38520000, 0x38524000, 0x38528000, 0x3852C000, 0x38530000, 0x38534000, 0x38538000, 0x3853C000,
+ 0x38540000, 0x38544000, 0x38548000, 0x3854C000, 0x38550000, 0x38554000, 0x38558000, 0x3855C000, 0x38560000, 0x38564000, 0x38568000, 0x3856C000, 0x38570000, 0x38574000, 0x38578000, 0x3857C000,
+ 0x38580000, 0x38584000, 0x38588000, 0x3858C000, 0x38590000, 0x38594000, 0x38598000, 0x3859C000, 0x385A0000, 0x385A4000, 0x385A8000, 0x385AC000, 0x385B0000, 0x385B4000, 0x385B8000, 0x385BC000,
+ 0x385C0000, 0x385C4000, 0x385C8000, 0x385CC000, 0x385D0000, 0x385D4000, 0x385D8000, 0x385DC000, 0x385E0000, 0x385E4000, 0x385E8000, 0x385EC000, 0x385F0000, 0x385F4000, 0x385F8000, 0x385FC000,
+ 0x38600000, 0x38604000, 0x38608000, 0x3860C000, 0x38610000, 0x38614000, 0x38618000, 0x3861C000, 0x38620000, 0x38624000, 0x38628000, 0x3862C000, 0x38630000, 0x38634000, 0x38638000, 0x3863C000,
+ 0x38640000, 0x38644000, 0x38648000, 0x3864C000, 0x38650000, 0x38654000, 0x38658000, 0x3865C000, 0x38660000, 0x38664000, 0x38668000, 0x3866C000, 0x38670000, 0x38674000, 0x38678000, 0x3867C000,
+ 0x38680000, 0x38684000, 0x38688000, 0x3868C000, 0x38690000, 0x38694000, 0x38698000, 0x3869C000, 0x386A0000, 0x386A4000, 0x386A8000, 0x386AC000, 0x386B0000, 0x386B4000, 0x386B8000, 0x386BC000,
+ 0x386C0000, 0x386C4000, 0x386C8000, 0x386CC000, 0x386D0000, 0x386D4000, 0x386D8000, 0x386DC000, 0x386E0000, 0x386E4000, 0x386E8000, 0x386EC000, 0x386F0000, 0x386F4000, 0x386F8000, 0x386FC000,
+ 0x38700000, 0x38704000, 0x38708000, 0x3870C000, 0x38710000, 0x38714000, 0x38718000, 0x3871C000, 0x38720000, 0x38724000, 0x38728000, 0x3872C000, 0x38730000, 0x38734000, 0x38738000, 0x3873C000,
+ 0x38740000, 0x38744000, 0x38748000, 0x3874C000, 0x38750000, 0x38754000, 0x38758000, 0x3875C000, 0x38760000, 0x38764000, 0x38768000, 0x3876C000, 0x38770000, 0x38774000, 0x38778000, 0x3877C000,
+ 0x38780000, 0x38784000, 0x38788000, 0x3878C000, 0x38790000, 0x38794000, 0x38798000, 0x3879C000, 0x387A0000, 0x387A4000, 0x387A8000, 0x387AC000, 0x387B0000, 0x387B4000, 0x387B8000, 0x387BC000,
+ 0x387C0000, 0x387C4000, 0x387C8000, 0x387CC000, 0x387D0000, 0x387D4000, 0x387D8000, 0x387DC000, 0x387E0000, 0x387E4000, 0x387E8000, 0x387EC000, 0x387F0000, 0x387F4000, 0x387F8000, 0x387FC000,
+ 0x38000000, 0x38002000, 0x38004000, 0x38006000, 0x38008000, 0x3800A000, 0x3800C000, 0x3800E000, 0x38010000, 0x38012000, 0x38014000, 0x38016000, 0x38018000, 0x3801A000, 0x3801C000, 0x3801E000,
+ 0x38020000, 0x38022000, 0x38024000, 0x38026000, 0x38028000, 0x3802A000, 0x3802C000, 0x3802E000, 0x38030000, 0x38032000, 0x38034000, 0x38036000, 0x38038000, 0x3803A000, 0x3803C000, 0x3803E000,
+ 0x38040000, 0x38042000, 0x38044000, 0x38046000, 0x38048000, 0x3804A000, 0x3804C000, 0x3804E000, 0x38050000, 0x38052000, 0x38054000, 0x38056000, 0x38058000, 0x3805A000, 0x3805C000, 0x3805E000,
+ 0x38060000, 0x38062000, 0x38064000, 0x38066000, 0x38068000, 0x3806A000, 0x3806C000, 0x3806E000, 0x38070000, 0x38072000, 0x38074000, 0x38076000, 0x38078000, 0x3807A000, 0x3807C000, 0x3807E000,
+ 0x38080000, 0x38082000, 0x38084000, 0x38086000, 0x38088000, 0x3808A000, 0x3808C000, 0x3808E000, 0x38090000, 0x38092000, 0x38094000, 0x38096000, 0x38098000, 0x3809A000, 0x3809C000, 0x3809E000,
+ 0x380A0000, 0x380A2000, 0x380A4000, 0x380A6000, 0x380A8000, 0x380AA000, 0x380AC000, 0x380AE000, 0x380B0000, 0x380B2000, 0x380B4000, 0x380B6000, 0x380B8000, 0x380BA000, 0x380BC000, 0x380BE000,
+ 0x380C0000, 0x380C2000, 0x380C4000, 0x380C6000, 0x380C8000, 0x380CA000, 0x380CC000, 0x380CE000, 0x380D0000, 0x380D2000, 0x380D4000, 0x380D6000, 0x380D8000, 0x380DA000, 0x380DC000, 0x380DE000,
+ 0x380E0000, 0x380E2000, 0x380E4000, 0x380E6000, 0x380E8000, 0x380EA000, 0x380EC000, 0x380EE000, 0x380F0000, 0x380F2000, 0x380F4000, 0x380F6000, 0x380F8000, 0x380FA000, 0x380FC000, 0x380FE000,
+ 0x38100000, 0x38102000, 0x38104000, 0x38106000, 0x38108000, 0x3810A000, 0x3810C000, 0x3810E000, 0x38110000, 0x38112000, 0x38114000, 0x38116000, 0x38118000, 0x3811A000, 0x3811C000, 0x3811E000,
+ 0x38120000, 0x38122000, 0x38124000, 0x38126000, 0x38128000, 0x3812A000, 0x3812C000, 0x3812E000, 0x38130000, 0x38132000, 0x38134000, 0x38136000, 0x38138000, 0x3813A000, 0x3813C000, 0x3813E000,
+ 0x38140000, 0x38142000, 0x38144000, 0x38146000, 0x38148000, 0x3814A000, 0x3814C000, 0x3814E000, 0x38150000, 0x38152000, 0x38154000, 0x38156000, 0x38158000, 0x3815A000, 0x3815C000, 0x3815E000,
+ 0x38160000, 0x38162000, 0x38164000, 0x38166000, 0x38168000, 0x3816A000, 0x3816C000, 0x3816E000, 0x38170000, 0x38172000, 0x38174000, 0x38176000, 0x38178000, 0x3817A000, 0x3817C000, 0x3817E000,
+ 0x38180000, 0x38182000, 0x38184000, 0x38186000, 0x38188000, 0x3818A000, 0x3818C000, 0x3818E000, 0x38190000, 0x38192000, 0x38194000, 0x38196000, 0x38198000, 0x3819A000, 0x3819C000, 0x3819E000,
+ 0x381A0000, 0x381A2000, 0x381A4000, 0x381A6000, 0x381A8000, 0x381AA000, 0x381AC000, 0x381AE000, 0x381B0000, 0x381B2000, 0x381B4000, 0x381B6000, 0x381B8000, 0x381BA000, 0x381BC000, 0x381BE000,
+ 0x381C0000, 0x381C2000, 0x381C4000, 0x381C6000, 0x381C8000, 0x381CA000, 0x381CC000, 0x381CE000, 0x381D0000, 0x381D2000, 0x381D4000, 0x381D6000, 0x381D8000, 0x381DA000, 0x381DC000, 0x381DE000,
+ 0x381E0000, 0x381E2000, 0x381E4000, 0x381E6000, 0x381E8000, 0x381EA000, 0x381EC000, 0x381EE000, 0x381F0000, 0x381F2000, 0x381F4000, 0x381F6000, 0x381F8000, 0x381FA000, 0x381FC000, 0x381FE000,
+ 0x38200000, 0x38202000, 0x38204000, 0x38206000, 0x38208000, 0x3820A000, 0x3820C000, 0x3820E000, 0x38210000, 0x38212000, 0x38214000, 0x38216000, 0x38218000, 0x3821A000, 0x3821C000, 0x3821E000,
+ 0x38220000, 0x38222000, 0x38224000, 0x38226000, 0x38228000, 0x3822A000, 0x3822C000, 0x3822E000, 0x38230000, 0x38232000, 0x38234000, 0x38236000, 0x38238000, 0x3823A000, 0x3823C000, 0x3823E000,
+ 0x38240000, 0x38242000, 0x38244000, 0x38246000, 0x38248000, 0x3824A000, 0x3824C000, 0x3824E000, 0x38250000, 0x38252000, 0x38254000, 0x38256000, 0x38258000, 0x3825A000, 0x3825C000, 0x3825E000,
+ 0x38260000, 0x38262000, 0x38264000, 0x38266000, 0x38268000, 0x3826A000, 0x3826C000, 0x3826E000, 0x38270000, 0x38272000, 0x38274000, 0x38276000, 0x38278000, 0x3827A000, 0x3827C000, 0x3827E000,
+ 0x38280000, 0x38282000, 0x38284000, 0x38286000, 0x38288000, 0x3828A000, 0x3828C000, 0x3828E000, 0x38290000, 0x38292000, 0x38294000, 0x38296000, 0x38298000, 0x3829A000, 0x3829C000, 0x3829E000,
+ 0x382A0000, 0x382A2000, 0x382A4000, 0x382A6000, 0x382A8000, 0x382AA000, 0x382AC000, 0x382AE000, 0x382B0000, 0x382B2000, 0x382B4000, 0x382B6000, 0x382B8000, 0x382BA000, 0x382BC000, 0x382BE000,
+ 0x382C0000, 0x382C2000, 0x382C4000, 0x382C6000, 0x382C8000, 0x382CA000, 0x382CC000, 0x382CE000, 0x382D0000, 0x382D2000, 0x382D4000, 0x382D6000, 0x382D8000, 0x382DA000, 0x382DC000, 0x382DE000,
+ 0x382E0000, 0x382E2000, 0x382E4000, 0x382E6000, 0x382E8000, 0x382EA000, 0x382EC000, 0x382EE000, 0x382F0000, 0x382F2000, 0x382F4000, 0x382F6000, 0x382F8000, 0x382FA000, 0x382FC000, 0x382FE000,
+ 0x38300000, 0x38302000, 0x38304000, 0x38306000, 0x38308000, 0x3830A000, 0x3830C000, 0x3830E000, 0x38310000, 0x38312000, 0x38314000, 0x38316000, 0x38318000, 0x3831A000, 0x3831C000, 0x3831E000,
+ 0x38320000, 0x38322000, 0x38324000, 0x38326000, 0x38328000, 0x3832A000, 0x3832C000, 0x3832E000, 0x38330000, 0x38332000, 0x38334000, 0x38336000, 0x38338000, 0x3833A000, 0x3833C000, 0x3833E000,
+ 0x38340000, 0x38342000, 0x38344000, 0x38346000, 0x38348000, 0x3834A000, 0x3834C000, 0x3834E000, 0x38350000, 0x38352000, 0x38354000, 0x38356000, 0x38358000, 0x3835A000, 0x3835C000, 0x3835E000,
+ 0x38360000, 0x38362000, 0x38364000, 0x38366000, 0x38368000, 0x3836A000, 0x3836C000, 0x3836E000, 0x38370000, 0x38372000, 0x38374000, 0x38376000, 0x38378000, 0x3837A000, 0x3837C000, 0x3837E000,
+ 0x38380000, 0x38382000, 0x38384000, 0x38386000, 0x38388000, 0x3838A000, 0x3838C000, 0x3838E000, 0x38390000, 0x38392000, 0x38394000, 0x38396000, 0x38398000, 0x3839A000, 0x3839C000, 0x3839E000,
+ 0x383A0000, 0x383A2000, 0x383A4000, 0x383A6000, 0x383A8000, 0x383AA000, 0x383AC000, 0x383AE000, 0x383B0000, 0x383B2000, 0x383B4000, 0x383B6000, 0x383B8000, 0x383BA000, 0x383BC000, 0x383BE000,
+ 0x383C0000, 0x383C2000, 0x383C4000, 0x383C6000, 0x383C8000, 0x383CA000, 0x383CC000, 0x383CE000, 0x383D0000, 0x383D2000, 0x383D4000, 0x383D6000, 0x383D8000, 0x383DA000, 0x383DC000, 0x383DE000,
+ 0x383E0000, 0x383E2000, 0x383E4000, 0x383E6000, 0x383E8000, 0x383EA000, 0x383EC000, 0x383EE000, 0x383F0000, 0x383F2000, 0x383F4000, 0x383F6000, 0x383F8000, 0x383FA000, 0x383FC000, 0x383FE000,
+ 0x38400000, 0x38402000, 0x38404000, 0x38406000, 0x38408000, 0x3840A000, 0x3840C000, 0x3840E000, 0x38410000, 0x38412000, 0x38414000, 0x38416000, 0x38418000, 0x3841A000, 0x3841C000, 0x3841E000,
+ 0x38420000, 0x38422000, 0x38424000, 0x38426000, 0x38428000, 0x3842A000, 0x3842C000, 0x3842E000, 0x38430000, 0x38432000, 0x38434000, 0x38436000, 0x38438000, 0x3843A000, 0x3843C000, 0x3843E000,
+ 0x38440000, 0x38442000, 0x38444000, 0x38446000, 0x38448000, 0x3844A000, 0x3844C000, 0x3844E000, 0x38450000, 0x38452000, 0x38454000, 0x38456000, 0x38458000, 0x3845A000, 0x3845C000, 0x3845E000,
+ 0x38460000, 0x38462000, 0x38464000, 0x38466000, 0x38468000, 0x3846A000, 0x3846C000, 0x3846E000, 0x38470000, 0x38472000, 0x38474000, 0x38476000, 0x38478000, 0x3847A000, 0x3847C000, 0x3847E000,
+ 0x38480000, 0x38482000, 0x38484000, 0x38486000, 0x38488000, 0x3848A000, 0x3848C000, 0x3848E000, 0x38490000, 0x38492000, 0x38494000, 0x38496000, 0x38498000, 0x3849A000, 0x3849C000, 0x3849E000,
+ 0x384A0000, 0x384A2000, 0x384A4000, 0x384A6000, 0x384A8000, 0x384AA000, 0x384AC000, 0x384AE000, 0x384B0000, 0x384B2000, 0x384B4000, 0x384B6000, 0x384B8000, 0x384BA000, 0x384BC000, 0x384BE000,
+ 0x384C0000, 0x384C2000, 0x384C4000, 0x384C6000, 0x384C8000, 0x384CA000, 0x384CC000, 0x384CE000, 0x384D0000, 0x384D2000, 0x384D4000, 0x384D6000, 0x384D8000, 0x384DA000, 0x384DC000, 0x384DE000,
+ 0x384E0000, 0x384E2000, 0x384E4000, 0x384E6000, 0x384E8000, 0x384EA000, 0x384EC000, 0x384EE000, 0x384F0000, 0x384F2000, 0x384F4000, 0x384F6000, 0x384F8000, 0x384FA000, 0x384FC000, 0x384FE000,
+ 0x38500000, 0x38502000, 0x38504000, 0x38506000, 0x38508000, 0x3850A000, 0x3850C000, 0x3850E000, 0x38510000, 0x38512000, 0x38514000, 0x38516000, 0x38518000, 0x3851A000, 0x3851C000, 0x3851E000,
+ 0x38520000, 0x38522000, 0x38524000, 0x38526000, 0x38528000, 0x3852A000, 0x3852C000, 0x3852E000, 0x38530000, 0x38532000, 0x38534000, 0x38536000, 0x38538000, 0x3853A000, 0x3853C000, 0x3853E000,
+ 0x38540000, 0x38542000, 0x38544000, 0x38546000, 0x38548000, 0x3854A000, 0x3854C000, 0x3854E000, 0x38550000, 0x38552000, 0x38554000, 0x38556000, 0x38558000, 0x3855A000, 0x3855C000, 0x3855E000,
+ 0x38560000, 0x38562000, 0x38564000, 0x38566000, 0x38568000, 0x3856A000, 0x3856C000, 0x3856E000, 0x38570000, 0x38572000, 0x38574000, 0x38576000, 0x38578000, 0x3857A000, 0x3857C000, 0x3857E000,
+ 0x38580000, 0x38582000, 0x38584000, 0x38586000, 0x38588000, 0x3858A000, 0x3858C000, 0x3858E000, 0x38590000, 0x38592000, 0x38594000, 0x38596000, 0x38598000, 0x3859A000, 0x3859C000, 0x3859E000,
+ 0x385A0000, 0x385A2000, 0x385A4000, 0x385A6000, 0x385A8000, 0x385AA000, 0x385AC000, 0x385AE000, 0x385B0000, 0x385B2000, 0x385B4000, 0x385B6000, 0x385B8000, 0x385BA000, 0x385BC000, 0x385BE000,
+ 0x385C0000, 0x385C2000, 0x385C4000, 0x385C6000, 0x385C8000, 0x385CA000, 0x385CC000, 0x385CE000, 0x385D0000, 0x385D2000, 0x385D4000, 0x385D6000, 0x385D8000, 0x385DA000, 0x385DC000, 0x385DE000,
+ 0x385E0000, 0x385E2000, 0x385E4000, 0x385E6000, 0x385E8000, 0x385EA000, 0x385EC000, 0x385EE000, 0x385F0000, 0x385F2000, 0x385F4000, 0x385F6000, 0x385F8000, 0x385FA000, 0x385FC000, 0x385FE000,
+ 0x38600000, 0x38602000, 0x38604000, 0x38606000, 0x38608000, 0x3860A000, 0x3860C000, 0x3860E000, 0x38610000, 0x38612000, 0x38614000, 0x38616000, 0x38618000, 0x3861A000, 0x3861C000, 0x3861E000,
+ 0x38620000, 0x38622000, 0x38624000, 0x38626000, 0x38628000, 0x3862A000, 0x3862C000, 0x3862E000, 0x38630000, 0x38632000, 0x38634000, 0x38636000, 0x38638000, 0x3863A000, 0x3863C000, 0x3863E000,
+ 0x38640000, 0x38642000, 0x38644000, 0x38646000, 0x38648000, 0x3864A000, 0x3864C000, 0x3864E000, 0x38650000, 0x38652000, 0x38654000, 0x38656000, 0x38658000, 0x3865A000, 0x3865C000, 0x3865E000,
+ 0x38660000, 0x38662000, 0x38664000, 0x38666000, 0x38668000, 0x3866A000, 0x3866C000, 0x3866E000, 0x38670000, 0x38672000, 0x38674000, 0x38676000, 0x38678000, 0x3867A000, 0x3867C000, 0x3867E000,
+ 0x38680000, 0x38682000, 0x38684000, 0x38686000, 0x38688000, 0x3868A000, 0x3868C000, 0x3868E000, 0x38690000, 0x38692000, 0x38694000, 0x38696000, 0x38698000, 0x3869A000, 0x3869C000, 0x3869E000,
+ 0x386A0000, 0x386A2000, 0x386A4000, 0x386A6000, 0x386A8000, 0x386AA000, 0x386AC000, 0x386AE000, 0x386B0000, 0x386B2000, 0x386B4000, 0x386B6000, 0x386B8000, 0x386BA000, 0x386BC000, 0x386BE000,
+ 0x386C0000, 0x386C2000, 0x386C4000, 0x386C6000, 0x386C8000, 0x386CA000, 0x386CC000, 0x386CE000, 0x386D0000, 0x386D2000, 0x386D4000, 0x386D6000, 0x386D8000, 0x386DA000, 0x386DC000, 0x386DE000,
+ 0x386E0000, 0x386E2000, 0x386E4000, 0x386E6000, 0x386E8000, 0x386EA000, 0x386EC000, 0x386EE000, 0x386F0000, 0x386F2000, 0x386F4000, 0x386F6000, 0x386F8000, 0x386FA000, 0x386FC000, 0x386FE000,
+ 0x38700000, 0x38702000, 0x38704000, 0x38706000, 0x38708000, 0x3870A000, 0x3870C000, 0x3870E000, 0x38710000, 0x38712000, 0x38714000, 0x38716000, 0x38718000, 0x3871A000, 0x3871C000, 0x3871E000,
+ 0x38720000, 0x38722000, 0x38724000, 0x38726000, 0x38728000, 0x3872A000, 0x3872C000, 0x3872E000, 0x38730000, 0x38732000, 0x38734000, 0x38736000, 0x38738000, 0x3873A000, 0x3873C000, 0x3873E000,
+ 0x38740000, 0x38742000, 0x38744000, 0x38746000, 0x38748000, 0x3874A000, 0x3874C000, 0x3874E000, 0x38750000, 0x38752000, 0x38754000, 0x38756000, 0x38758000, 0x3875A000, 0x3875C000, 0x3875E000,
+ 0x38760000, 0x38762000, 0x38764000, 0x38766000, 0x38768000, 0x3876A000, 0x3876C000, 0x3876E000, 0x38770000, 0x38772000, 0x38774000, 0x38776000, 0x38778000, 0x3877A000, 0x3877C000, 0x3877E000,
+ 0x38780000, 0x38782000, 0x38784000, 0x38786000, 0x38788000, 0x3878A000, 0x3878C000, 0x3878E000, 0x38790000, 0x38792000, 0x38794000, 0x38796000, 0x38798000, 0x3879A000, 0x3879C000, 0x3879E000,
+ 0x387A0000, 0x387A2000, 0x387A4000, 0x387A6000, 0x387A8000, 0x387AA000, 0x387AC000, 0x387AE000, 0x387B0000, 0x387B2000, 0x387B4000, 0x387B6000, 0x387B8000, 0x387BA000, 0x387BC000, 0x387BE000,
+ 0x387C0000, 0x387C2000, 0x387C4000, 0x387C6000, 0x387C8000, 0x387CA000, 0x387CC000, 0x387CE000, 0x387D0000, 0x387D2000, 0x387D4000, 0x387D6000, 0x387D8000, 0x387DA000, 0x387DC000, 0x387DE000,
+ 0x387E0000, 0x387E2000, 0x387E4000, 0x387E6000, 0x387E8000, 0x387EA000, 0x387EC000, 0x387EE000, 0x387F0000, 0x387F2000, 0x387F4000, 0x387F6000, 0x387F8000, 0x387FA000, 0x387FC000, 0x387FE000 };
+ static const uint32 exponent_table[64] = {
+ 0x00000000, 0x00800000, 0x01000000, 0x01800000, 0x02000000, 0x02800000, 0x03000000, 0x03800000, 0x04000000, 0x04800000, 0x05000000, 0x05800000, 0x06000000, 0x06800000, 0x07000000, 0x07800000,
+ 0x08000000, 0x08800000, 0x09000000, 0x09800000, 0x0A000000, 0x0A800000, 0x0B000000, 0x0B800000, 0x0C000000, 0x0C800000, 0x0D000000, 0x0D800000, 0x0E000000, 0x0E800000, 0x0F000000, 0x47800000,
+ 0x80000000, 0x80800000, 0x81000000, 0x81800000, 0x82000000, 0x82800000, 0x83000000, 0x83800000, 0x84000000, 0x84800000, 0x85000000, 0x85800000, 0x86000000, 0x86800000, 0x87000000, 0x87800000,
+ 0x88000000, 0x88800000, 0x89000000, 0x89800000, 0x8A000000, 0x8A800000, 0x8B000000, 0x8B800000, 0x8C000000, 0x8C800000, 0x8D000000, 0x8D800000, 0x8E000000, 0x8E800000, 0x8F000000, 0xC7800000 };
+ static const unsigned short offset_table[64] = {
+ 0, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
+ 0, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024 };
+ uint32 bits = mantissa_table[offset_table[value>>10]+(value&0x3FF)] + exponent_table[value>>10];
+// return *reinterpret_cast<float*>(&bits); //violating strict aliasing!
+ float out;
+ std::memcpy(&out, &bits, sizeof(float));
+ return out;
+ }
+
+ /// Convert half-precision to IEEE double-precision.
+ /// \param value binary representation of half-precision value
+ /// \return double-precision value
+ inline double half2float_impl(uint16 value, double, true_type)
+ {
+ typedef bits<float>::type uint32;
+ typedef bits<double>::type uint64;
+ uint32 hi = static_cast<uint32>(value&0x8000) << 16;
+ int abs = value & 0x7FFF;
+ if(abs)
+ {
+ hi |= 0x3F000000 << static_cast<unsigned>(abs>=0x7C00);
+ for(; abs<0x400; abs<<=1,hi-=0x100000) ;
+ hi += static_cast<uint32>(abs) << 10;
+ }
+ uint64 bits = static_cast<uint64>(hi) << 32;
+// return *reinterpret_cast<double*>(&bits); //violating strict aliasing!
+ double out;
+ std::memcpy(&out, &bits, sizeof(double));
+ return out;
+ }
+
+ /// Convert half-precision to non-IEEE floating point.
+ /// \tparam T type to convert to (builtin integer type)
+ /// \param value binary representation of half-precision value
+ /// \return floating point value
+ template<typename T> T half2float_impl(uint16 value, T, ...)
+ {
+ T out;
+ int abs = value & 0x7FFF;
+ if(abs > 0x7C00)
+ out = std::numeric_limits<T>::has_quiet_NaN ? std::numeric_limits<T>::quiet_NaN() : T();
+ else if(abs == 0x7C00)
+ out = std::numeric_limits<T>::has_infinity ? std::numeric_limits<T>::infinity() : std::numeric_limits<T>::max();
+ else if(abs > 0x3FF)
+ out = std::ldexp(static_cast<T>((abs&0x3FF)|0x400), (abs>>10)-25);
+ else
+ out = std::ldexp(static_cast<T>(abs), -24);
+ return (value&0x8000) ? -out : out;
+ }
+
+ /// Convert half-precision to floating point.
+ /// \tparam T type to convert to (builtin integer type)
+ /// \param value binary representation of half-precision value
+ /// \return floating point value
+ template<typename T> T half2float(uint16 value)
+ {
+ return half2float_impl(value, T(), bool_type<std::numeric_limits<T>::is_iec559&&sizeof(typename bits<T>::type)==sizeof(T)>());
+ }
+
+ /// Convert half-precision floating point to integer.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam E `true` for round to even, `false` for round away from zero
+ /// \tparam T type to convert to (buitlin integer type with at least 16 bits precision, excluding any implicit sign bits)
+ /// \param value binary representation of half-precision value
+ /// \return integral value
+ template<std::float_round_style R,bool E,typename T> T half2int_impl(uint16 value)
+ {
+ #if HALF_ENABLE_CPP11_STATIC_ASSERT && HALF_ENABLE_CPP11_TYPE_TRAITS
+ static_assert(std::is_integral<T>::value, "half to int conversion only supports builtin integer types");
+ #endif
+ unsigned int e = value & 0x7FFF;
+ if(e >= 0x7C00)
+ return (value&0x8000) ? std::numeric_limits<T>::min() : std::numeric_limits<T>::max();
+ if(e < 0x3800)
+ {
+ if(R == std::round_toward_infinity)
+ return T(~(value>>15)&(e!=0));
+ else if(R == std::round_toward_neg_infinity)
+ return -T(value>0x8000);
+ return T();
+ }
+ unsigned int m = (value&0x3FF) | 0x400;
+ e >>= 10;
+ if(e < 25)
+ {
+ if(R == std::round_to_nearest)
+ m += (1<<(24-e)) - (~(m>>(25-e))&E);
+ else if(R == std::round_toward_infinity)
+ m += ((value>>15)-1) & ((1<<(25-e))-1U);
+ else if(R == std::round_toward_neg_infinity)
+ m += -(value>>15) & ((1<<(25-e))-1U);
+ m >>= 25 - e;
+ }
+ else
+ m <<= e - 25;
+ return (value&0x8000) ? -static_cast<T>(m) : static_cast<T>(m);
+ }
+
+ /// Convert half-precision floating point to integer.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam T type to convert to (buitlin integer type with at least 16 bits precision, excluding any implicit sign bits)
+ /// \param value binary representation of half-precision value
+ /// \return integral value
+ template<std::float_round_style R,typename T> T half2int(uint16 value) { return half2int_impl<R,HALF_ROUND_TIES_TO_EVEN,T>(value); }
+
+ /// Convert half-precision floating point to integer using round-to-nearest-away-from-zero.
+ /// \tparam T type to convert to (buitlin integer type with at least 16 bits precision, excluding any implicit sign bits)
+ /// \param value binary representation of half-precision value
+ /// \return integral value
+ template<typename T> T half2int_up(uint16 value) { return half2int_impl<std::round_to_nearest,0,T>(value); }
+
+ /// Round half-precision number to nearest integer value.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \tparam E `true` for round to even, `false` for round away from zero
+ /// \param value binary representation of half-precision value
+ /// \return half-precision bits for nearest integral value
+ template<std::float_round_style R,bool E> uint16 round_half_impl(uint16 value)
+ {
+ unsigned int e = value & 0x7FFF;
+ uint16 result = value;
+ if(e < 0x3C00)
+ {
+ result &= 0x8000;
+ if(R == std::round_to_nearest)
+ result |= 0x3C00U & -(e>=(0x3800+E));
+ else if(R == std::round_toward_infinity)
+ result |= 0x3C00U & -(~(value>>15)&(e!=0));
+ else if(R == std::round_toward_neg_infinity)
+ result |= 0x3C00U & -(value>0x8000);
+ }
+ else if(e < 0x6400)
+ {
+ e = 25 - (e>>10);
+ unsigned int mask = (1<<e) - 1;
+ if(R == std::round_to_nearest)
+ result += (1<<(e-1)) - (~(result>>e)&E);
+ else if(R == std::round_toward_infinity)
+ result += mask & ((value>>15)-1);
+ else if(R == std::round_toward_neg_infinity)
+ result += mask & -(value>>15);
+ result &= ~mask;
+ }
+ return result;
+ }
+
+ /// Round half-precision number to nearest integer value.
+ /// \tparam R rounding mode to use, `std::round_indeterminate` for fastest rounding
+ /// \param value binary representation of half-precision value
+ /// \return half-precision bits for nearest integral value
+ template<std::float_round_style R> uint16 round_half(uint16 value) { return round_half_impl<R,HALF_ROUND_TIES_TO_EVEN>(value); }
+
+ /// Round half-precision number to nearest integer value using round-to-nearest-away-from-zero.
+ /// \param value binary representation of half-precision value
+ /// \return half-precision bits for nearest integral value
+ inline uint16 round_half_up(uint16 value) { return round_half_impl<std::round_to_nearest,0>(value); }
+ /// \}
+
+ struct functions;
+ template<typename> struct unary_specialized;
+ template<typename,typename> struct binary_specialized;
+ template<typename,typename,std::float_round_style> struct half_caster;
+ }
+
+ /// Half-precision floating point type.
+ /// This class implements an IEEE-conformant half-precision floating point type with the usual arithmetic operators and
+ /// conversions. It is implicitly convertible to single-precision floating point, which makes artihmetic expressions and
+ /// functions with mixed-type operands to be of the most precise operand type. Additionally all arithmetic operations
+ /// (and many mathematical functions) are carried out in single-precision internally. All conversions from single- to
+ /// half-precision are done using the library's default rounding mode, but temporary results inside chained arithmetic
+ /// expressions are kept in single-precision as long as possible (while of course still maintaining a strong half-precision type).
+ ///
+ /// According to the C++98/03 definition, the half type is not a POD type. But according to C++11's less strict and
+ /// extended definitions it is both a standard layout type and a trivially copyable type (even if not a POD type), which
+ /// means it can be standard-conformantly copied using raw binary copies. But in this context some more words about the
+ /// actual size of the type. Although the half is representing an IEEE 16-bit type, it does not neccessarily have to be of
+ /// exactly 16-bits size. But on any reasonable implementation the actual binary representation of this type will most
+ /// probably not ivolve any additional "magic" or padding beyond the simple binary representation of the underlying 16-bit
+ /// IEEE number, even if not strictly guaranteed by the standard. But even then it only has an actual size of 16 bits if
+ /// your C++ implementation supports an unsigned integer type of exactly 16 bits width. But this should be the case on
+ /// nearly any reasonable platform.
+ ///
+ /// So if your C++ implementation is not totally exotic or imposes special alignment requirements, it is a reasonable
+ /// assumption that the data of a half is just comprised of the 2 bytes of the underlying IEEE representation.
+ class half
+ {
+ friend struct detail::functions;
+ friend struct detail::unary_specialized<half>;
+ friend struct detail::binary_specialized<half,half>;
+ template<typename,typename,std::float_round_style> friend struct detail::half_caster;
+ friend class std::numeric_limits<half>;
+ #if HALF_ENABLE_CPP11_HASH
+ friend struct std::hash<half>;
+ #endif
+ #if HALF_ENABLE_CPP11_USER_LITERALS
+ friend half literal::operator"" _h(long double);
+ #endif
+
+ public:
+ /// Default constructor.
+ /// This initializes the half to 0. Although this does not match the builtin types' default-initialization semantics
+ /// and may be less efficient than no initialization, it is needed to provide proper value-initialization semantics.
+ HALF_CONSTEXPR half() HALF_NOEXCEPT : data_() {}
+
+ /// Copy constructor.
+ /// \tparam T type of concrete half expression
+ /// \param rhs half expression to copy from
+ half(detail::expr rhs) : data_(detail::float2half<round_style>(static_cast<float>(rhs))) {}
+
+ /// Conversion constructor.
+ /// \param rhs float to convert
+ explicit half(float rhs) : data_(detail::float2half<round_style>(rhs)) {}
+
+ /// Conversion to single-precision.
+ /// \return single precision value representing expression value
+ operator float() const { return detail::half2float<float>(data_); }
+
+ /// Assignment operator.
+ /// \tparam T type of concrete half expression
+ /// \param rhs half expression to copy from
+ /// \return reference to this half
+ half& operator=(detail::expr rhs) { return *this = static_cast<float>(rhs); }
+
+ /// Arithmetic assignment.
+ /// \tparam T type of concrete half expression
+ /// \param rhs half expression to add
+ /// \return reference to this half
+ template<typename T> typename detail::enable<half&,T>::type operator+=(T rhs) { return *this += static_cast<float>(rhs); }
+
+ /// Arithmetic assignment.
+ /// \tparam T type of concrete half expression
+ /// \param rhs half expression to subtract
+ /// \return reference to this half
+ template<typename T> typename detail::enable<half&,T>::type operator-=(T rhs) { return *this -= static_cast<float>(rhs); }
+
+ /// Arithmetic assignment.
+ /// \tparam T type of concrete half expression
+ /// \param rhs half expression to multiply with
+ /// \return reference to this half
+ template<typename T> typename detail::enable<half&,T>::type operator*=(T rhs) { return *this *= static_cast<float>(rhs); }
+
+ /// Arithmetic assignment.
+ /// \tparam T type of concrete half expression
+ /// \param rhs half expression to divide by
+ /// \return reference to this half
+ template<typename T> typename detail::enable<half&,T>::type operator/=(T rhs) { return *this /= static_cast<float>(rhs); }
+
+ /// Assignment operator.
+ /// \param rhs single-precision value to copy from
+ /// \return reference to this half
+ half& operator=(float rhs) { data_ = detail::float2half<round_style>(rhs); return *this; }
+
+ /// Arithmetic assignment.
+ /// \param rhs single-precision value to add
+ /// \return reference to this half
+ half& operator+=(float rhs) { data_ = detail::float2half<round_style>(detail::half2float<float>(data_)+rhs); return *this; }
+
+ /// Arithmetic assignment.
+ /// \param rhs single-precision value to subtract
+ /// \return reference to this half
+ half& operator-=(float rhs) { data_ = detail::float2half<round_style>(detail::half2float<float>(data_)-rhs); return *this; }
+
+ /// Arithmetic assignment.
+ /// \param rhs single-precision value to multiply with
+ /// \return reference to this half
+ half& operator*=(float rhs) { data_ = detail::float2half<round_style>(detail::half2float<float>(data_)*rhs); return *this; }
+
+ /// Arithmetic assignment.
+ /// \param rhs single-precision value to divide by
+ /// \return reference to this half
+ half& operator/=(float rhs) { data_ = detail::float2half<round_style>(detail::half2float<float>(data_)/rhs); return *this; }
+
+ /// Prefix increment.
+ /// \return incremented half value
+ half& operator++() { return *this += 1.0f; }
+
+ /// Prefix decrement.
+ /// \return decremented half value
+ half& operator--() { return *this -= 1.0f; }
+
+ /// Postfix increment.
+ /// \return non-incremented half value
+ half operator++(int) { half out(*this); ++*this; return out; }
+
+ /// Postfix decrement.
+ /// \return non-decremented half value
+ half operator--(int) { half out(*this); --*this; return out; }
+
+ private:
+ /// Rounding mode to use
+ static const std::float_round_style round_style = (std::float_round_style)(HALF_ROUND_STYLE);
+
+ /// Constructor.
+ /// \param bits binary representation to set half to
+ HALF_CONSTEXPR half(detail::binary_t, detail::uint16 bits) HALF_NOEXCEPT : data_(bits) {}
+
+ /// Internal binary representation
+ detail::uint16 data_;
+ };
+
+#if HALF_ENABLE_CPP11_USER_LITERALS
+ namespace literal
+ {
+ /// Half literal.
+ /// While this returns an actual half-precision value, half literals can unfortunately not be constant expressions due
+ /// to rather involved conversions.
+ /// \param value literal value
+ /// \return half with given value (if representable)
+ inline half operator"" _h(long double value) { return half(detail::binary, detail::float2half<half::round_style>(value)); }
+ }
+#endif
+
+ namespace detail
+ {
+ /// Wrapper implementing unspecialized half-precision functions.
+ struct functions
+ {
+ /// Addition implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Half-precision sum stored in single-precision
+ static expr plus(float x, float y) { return expr(x+y); }
+
+ /// Subtraction implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Half-precision difference stored in single-precision
+ static expr minus(float x, float y) { return expr(x-y); }
+
+ /// Multiplication implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Half-precision product stored in single-precision
+ static expr multiplies(float x, float y) { return expr(x*y); }
+
+ /// Division implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Half-precision quotient stored in single-precision
+ static expr divides(float x, float y) { return expr(x/y); }
+
+ /// Output implementation.
+ /// \param out stream to write to
+ /// \param arg value to write
+ /// \return reference to stream
+ template<typename charT,typename traits> static std::basic_ostream<charT,traits>& write(std::basic_ostream<charT,traits> &out, float arg) { return out << arg; }
+
+ /// Input implementation.
+ /// \param in stream to read from
+ /// \param arg half to read into
+ /// \return reference to stream
+ template<typename charT,typename traits> static std::basic_istream<charT,traits>& read(std::basic_istream<charT,traits> &in, half &arg)
+ {
+ float f;
+ if(in >> f)
+ arg = f;
+ return in;
+ }
+
+ /// Modulo implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Half-precision division remainder stored in single-precision
+ static expr fmod(float x, float y) { return expr(std::fmod(x, y)); }
+
+ /// Remainder implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Half-precision division remainder stored in single-precision
+ static expr remainder(float x, float y)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::remainder(x, y));
+ #else
+ if(builtin_isnan(x) || builtin_isnan(y))
+ return expr(std::numeric_limits<float>::quiet_NaN());
+ float ax = std::fabs(x), ay = std::fabs(y);
+ if(ax >= 65536.0f || ay < std::ldexp(1.0f, -24))
+ return expr(std::numeric_limits<float>::quiet_NaN());
+ if(ay >= 65536.0f)
+ return expr(x);
+ if(ax == ay)
+ return expr(builtin_signbit(x) ? -0.0f : 0.0f);
+ ax = std::fmod(ax, ay+ay);
+ float y2 = 0.5f * ay;
+ if(ax > y2)
+ {
+ ax -= ay;
+ if(ax >= y2)
+ ax -= ay;
+ }
+ return expr(builtin_signbit(x) ? -ax : ax);
+ #endif
+ }
+
+ /// Remainder implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \param quo address to store quotient bits at
+ /// \return Half-precision division remainder stored in single-precision
+ static expr remquo(float x, float y, int *quo)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::remquo(x, y, quo));
+ #else
+ if(builtin_isnan(x) || builtin_isnan(y))
+ return expr(std::numeric_limits<float>::quiet_NaN());
+ bool sign = builtin_signbit(x), qsign = static_cast<bool>(sign^builtin_signbit(y));
+ float ax = std::fabs(x), ay = std::fabs(y);
+ if(ax >= 65536.0f || ay < std::ldexp(1.0f, -24))
+ return expr(std::numeric_limits<float>::quiet_NaN());
+ if(ay >= 65536.0f)
+ return expr(x);
+ if(ax == ay)
+ return *quo = qsign ? -1 : 1, expr(sign ? -0.0f : 0.0f);
+ ax = std::fmod(ax, 8.0f*ay);
+ int cquo = 0;
+ if(ax >= 4.0f * ay)
+ {
+ ax -= 4.0f * ay;
+ cquo += 4;
+ }
+ if(ax >= 2.0f * ay)
+ {
+ ax -= 2.0f * ay;
+ cquo += 2;
+ }
+ float y2 = 0.5f * ay;
+ if(ax > y2)
+ {
+ ax -= ay;
+ ++cquo;
+ if(ax >= y2)
+ {
+ ax -= ay;
+ ++cquo;
+ }
+ }
+ return *quo = qsign ? -cquo : cquo, expr(sign ? -ax : ax);
+ #endif
+ }
+
+ /// Positive difference implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return Positive difference stored in single-precision
+ static expr fdim(float x, float y)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::fdim(x, y));
+ #else
+ return expr((x<=y) ? 0.0f : (x-y));
+ #endif
+ }
+
+ /// Fused multiply-add implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \param z third operand
+ /// \return \a x * \a y + \a z stored in single-precision
+ static expr fma(float x, float y, float z)
+ {
+ #if HALF_ENABLE_CPP11_CMATH && defined(FP_FAST_FMAF)
+ return expr(std::fma(x, y, z));
+ #else
+ return expr(x*y+z);
+ #endif
+ }
+
+ /// Get NaN.
+ /// \return Half-precision quiet NaN
+ static half nanh() { return half(binary, 0x7FFF); }
+
+ /// Exponential implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr exp(float arg) { return expr(std::exp(arg)); }
+
+ /// Exponential implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr expm1(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::expm1(arg));
+ #else
+ return expr(static_cast<float>(std::exp(static_cast<double>(arg))-1.0));
+ #endif
+ }
+
+ /// Binary exponential implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr exp2(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::exp2(arg));
+ #else
+ return expr(static_cast<float>(std::exp(arg*0.69314718055994530941723212145818)));
+ #endif
+ }
+
+ /// Logarithm implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr log(float arg) { return expr(std::log(arg)); }
+
+ /// Common logarithm implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr log10(float arg) { return expr(std::log10(arg)); }
+
+ /// Logarithm implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr log1p(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::log1p(arg));
+ #else
+ return expr(static_cast<float>(std::log(1.0+arg)));
+ #endif
+ }
+
+ /// Binary logarithm implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr log2(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::log2(arg));
+ #else
+ return expr(static_cast<float>(std::log(static_cast<double>(arg))*1.4426950408889634073599246810019));
+ #endif
+ }
+
+ /// Square root implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr sqrt(float arg) { return expr(std::sqrt(arg)); }
+
+ /// Cubic root implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr cbrt(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::cbrt(arg));
+ #else
+ if(builtin_isnan(arg) || builtin_isinf(arg))
+ return expr(arg);
+ return expr(builtin_signbit(arg) ? -static_cast<float>(std::pow(-static_cast<double>(arg), 1.0/3.0)) :
+ static_cast<float>(std::pow(static_cast<double>(arg), 1.0/3.0)));
+ #endif
+ }
+
+ /// Hypotenuse implementation.
+ /// \param x first argument
+ /// \param y second argument
+ /// \return function value stored in single-preicision
+ static expr hypot(float x, float y)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::hypot(x, y));
+ #else
+ return expr((builtin_isinf(x) || builtin_isinf(y)) ? std::numeric_limits<float>::infinity() :
+ static_cast<float>(std::sqrt(static_cast<double>(x)*x+static_cast<double>(y)*y)));
+ #endif
+ }
+
+ /// Power implementation.
+ /// \param base value to exponentiate
+ /// \param exp power to expontiate to
+ /// \return function value stored in single-preicision
+ static expr pow(float base, float exp) { return expr(std::pow(base, exp)); }
+
+ /// Sine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr sin(float arg) { return expr(std::sin(arg)); }
+
+ /// Cosine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr cos(float arg) { return expr(std::cos(arg)); }
+
+ /// Tan implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr tan(float arg) { return expr(std::tan(arg)); }
+
+ /// Arc sine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr asin(float arg) { return expr(std::asin(arg)); }
+
+ /// Arc cosine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr acos(float arg) { return expr(std::acos(arg)); }
+
+ /// Arc tangent implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr atan(float arg) { return expr(std::atan(arg)); }
+
+ /// Arc tangent implementation.
+ /// \param x first argument
+ /// \param y second argument
+ /// \return function value stored in single-preicision
+ static expr atan2(float x, float y) { return expr(std::atan2(x, y)); }
+
+ /// Hyperbolic sine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr sinh(float arg) { return expr(std::sinh(arg)); }
+
+ /// Hyperbolic cosine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr cosh(float arg) { return expr(std::cosh(arg)); }
+
+ /// Hyperbolic tangent implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr tanh(float arg) { return expr(std::tanh(arg)); }
+
+ /// Hyperbolic area sine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr asinh(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::asinh(arg));
+ #else
+ return expr((arg==-std::numeric_limits<float>::infinity()) ? arg : static_cast<float>(std::log(arg+std::sqrt(arg*arg+1.0))));
+ #endif
+ }
+
+ /// Hyperbolic area cosine implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr acosh(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::acosh(arg));
+ #else
+ return expr((arg<-1.0f) ? std::numeric_limits<float>::quiet_NaN() : static_cast<float>(std::log(arg+std::sqrt(arg*arg-1.0))));
+ #endif
+ }
+
+ /// Hyperbolic area tangent implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr atanh(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::atanh(arg));
+ #else
+ return expr(static_cast<float>(0.5*std::log((1.0+arg)/(1.0-arg))));
+ #endif
+ }
+
+ /// Error function implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr erf(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::erf(arg));
+ #else
+ return expr(static_cast<float>(erf(static_cast<double>(arg))));
+ #endif
+ }
+
+ /// Complementary implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr erfc(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::erfc(arg));
+ #else
+ return expr(static_cast<float>(1.0-erf(static_cast<double>(arg))));
+ #endif
+ }
+
+ /// Gamma logarithm implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr lgamma(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::lgamma(arg));
+ #else
+ if(builtin_isinf(arg))
+ return expr(std::numeric_limits<float>::infinity());
+ if(arg < 0.0f)
+ {
+ float i, f = std::modf(-arg, &i);
+ if(f == 0.0f)
+ return expr(std::numeric_limits<float>::infinity());
+ return expr(static_cast<float>(1.1447298858494001741434273513531-
+ std::log(std::abs(std::sin(3.1415926535897932384626433832795*f)))-lgamma(1.0-arg)));
+ }
+ return expr(static_cast<float>(lgamma(static_cast<double>(arg))));
+ #endif
+ }
+
+ /// Gamma implementation.
+ /// \param arg function argument
+ /// \return function value stored in single-preicision
+ static expr tgamma(float arg)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::tgamma(arg));
+ #else
+ if(arg == 0.0f)
+ return builtin_signbit(arg) ? expr(-std::numeric_limits<float>::infinity()) : expr(std::numeric_limits<float>::infinity());
+ if(arg < 0.0f)
+ {
+ float i, f = std::modf(-arg, &i);
+ if(f == 0.0f)
+ return expr(std::numeric_limits<float>::quiet_NaN());
+ double value = 3.1415926535897932384626433832795 / (std::sin(3.1415926535897932384626433832795*f)*std::exp(lgamma(1.0-arg)));
+ return expr(static_cast<float>((std::fmod(i, 2.0f)==0.0f) ? -value : value));
+ }
+ if(builtin_isinf(arg))
+ return expr(arg);
+ return expr(static_cast<float>(std::exp(lgamma(static_cast<double>(arg)))));
+ #endif
+ }
+
+ /// Floor implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static half floor(half arg) { return half(binary, round_half<std::round_toward_neg_infinity>(arg.data_)); }
+
+ /// Ceiling implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static half ceil(half arg) { return half(binary, round_half<std::round_toward_infinity>(arg.data_)); }
+
+ /// Truncation implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static half trunc(half arg) { return half(binary, round_half<std::round_toward_zero>(arg.data_)); }
+
+ /// Nearest integer implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static half round(half arg) { return half(binary, round_half_up(arg.data_)); }
+
+ /// Nearest integer implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static long lround(half arg) { return detail::half2int_up<long>(arg.data_); }
+
+ /// Nearest integer implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static half rint(half arg) { return half(binary, round_half<half::round_style>(arg.data_)); }
+
+ /// Nearest integer implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static long lrint(half arg) { return detail::half2int<half::round_style,long>(arg.data_); }
+
+ #if HALF_ENABLE_CPP11_LONG_LONG
+ /// Nearest integer implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static long long llround(half arg) { return detail::half2int_up<long long>(arg.data_); }
+
+ /// Nearest integer implementation.
+ /// \param arg value to round
+ /// \return rounded value
+ static long long llrint(half arg) { return detail::half2int<half::round_style,long long>(arg.data_); }
+ #endif
+
+ /// Decompression implementation.
+ /// \param arg number to decompress
+ /// \param exp address to store exponent at
+ /// \return normalized significant
+ static half frexp(half arg, int *exp)
+ {
+ int m = arg.data_ & 0x7FFF, e = -14;
+ if(m >= 0x7C00 || !m)
+ return *exp = 0, arg;
+ for(; m<0x400; m<<=1,--e) ;
+ return *exp = e+(m>>10), half(binary, (arg.data_&0x8000)|0x3800|(m&0x3FF));
+ }
+
+ /// Decompression implementation.
+ /// \param arg number to decompress
+ /// \param iptr address to store integer part at
+ /// \return fractional part
+ static half modf(half arg, half *iptr)
+ {
+ unsigned int e = arg.data_ & 0x7FFF;
+ if(e >= 0x6400)
+ return *iptr = arg, half(binary, arg.data_&(0x8000U|-(e>0x7C00)));
+ if(e < 0x3C00)
+ return iptr->data_ = arg.data_ & 0x8000, arg;
+ e >>= 10;
+ unsigned int mask = (1<<(25-e)) - 1, m = arg.data_ & mask;
+ iptr->data_ = arg.data_ & ~mask;
+ if(!m)
+ return half(binary, arg.data_&0x8000);
+ for(; m<0x400; m<<=1,--e) ;
+ return half(binary, static_cast<uint16>((arg.data_&0x8000)|(e<<10)|(m&0x3FF)));
+ }
+
+ /// Scaling implementation.
+ /// \param arg number to scale
+ /// \param exp power of two to scale by
+ /// \return scaled number
+ static half scalbln(half arg, long exp)
+ {
+ unsigned int m = arg.data_ & 0x7FFF;
+ if(m >= 0x7C00 || !m)
+ return arg;
+ for(; m<0x400; m<<=1,--exp) ;
+ exp += m >> 10;
+ uint16 value = arg.data_ & 0x8000;
+ if(exp > 30)
+ {
+ if(half::round_style == std::round_toward_zero)
+ value |= 0x7BFF;
+ else if(half::round_style == std::round_toward_infinity)
+ value |= 0x7C00 - (value>>15);
+ else if(half::round_style == std::round_toward_neg_infinity)
+ value |= 0x7BFF + (value>>15);
+ else
+ value |= 0x7C00;
+ }
+ else if(exp > 0)
+ value |= (exp<<10) | (m&0x3FF);
+ else if(exp > -11)
+ {
+ m = (m&0x3FF) | 0x400;
+ if(half::round_style == std::round_to_nearest)
+ {
+ m += 1 << -exp;
+ #if HALF_ROUND_TIES_TO_EVEN
+ m -= (m>>(1-exp)) & 1;
+ #endif
+ }
+ else if(half::round_style == std::round_toward_infinity)
+ m += ((value>>15)-1) & ((1<<(1-exp))-1U);
+ else if(half::round_style == std::round_toward_neg_infinity)
+ m += -(value>>15) & ((1<<(1-exp))-1U);
+ value |= m >> (1-exp);
+ }
+ else if(half::round_style == std::round_toward_infinity)
+ value -= (value>>15) - 1;
+ else if(half::round_style == std::round_toward_neg_infinity)
+ value += value >> 15;
+ return half(binary, value);
+ }
+
+ /// Exponent implementation.
+ /// \param arg number to query
+ /// \return floating point exponent
+ static int ilogb(half arg)
+ {
+ int abs = arg.data_ & 0x7FFF;
+ if(!abs)
+ return FP_ILOGB0;
+ if(abs < 0x7C00)
+ {
+ int exp = (abs>>10) - 15;
+ if(abs < 0x400)
+ for(; abs<0x200; abs<<=1,--exp) ;
+ return exp;
+ }
+ if(abs > 0x7C00)
+ return FP_ILOGBNAN;
+ return INT_MAX;
+ }
+
+ /// Exponent implementation.
+ /// \param arg number to query
+ /// \return floating point exponent
+ static half logb(half arg)
+ {
+ int abs = arg.data_ & 0x7FFF;
+ if(!abs)
+ return half(binary, 0xFC00);
+ if(abs < 0x7C00)
+ {
+ int exp = (abs>>10) - 15;
+ if(abs < 0x400)
+ for(; abs<0x200; abs<<=1,--exp) ;
+ uint16 bits = (exp<0) << 15;
+ if(exp)
+ {
+ unsigned int m = std::abs(exp) << 6, e = 18;
+ for(; m<0x400; m<<=1,--e) ;
+ bits |= (e<<10) + m;
+ }
+ return half(binary, bits);
+ }
+ if(abs > 0x7C00)
+ return arg;
+ return half(binary, 0x7C00);
+ }
+
+ /// Enumeration implementation.
+ /// \param from number to increase/decrease
+ /// \param to direction to enumerate into
+ /// \return next representable number
+ static half nextafter(half from, half to)
+ {
+ uint16 fabs = from.data_ & 0x7FFF, tabs = to.data_ & 0x7FFF;
+ if(fabs > 0x7C00)
+ return from;
+ if(tabs > 0x7C00 || from.data_ == to.data_ || !(fabs|tabs))
+ return to;
+ if(!fabs)
+ return half(binary, (to.data_&0x8000)+1);
+ bool lt = ((fabs==from.data_) ? static_cast<int>(fabs) : -static_cast<int>(fabs)) <
+ ((tabs==to.data_) ? static_cast<int>(tabs) : -static_cast<int>(tabs));
+ return half(binary, from.data_+(((from.data_>>15)^static_cast<unsigned>(lt))<<1)-1);
+ }
+
+ /// Enumeration implementation.
+ /// \param from number to increase/decrease
+ /// \param to direction to enumerate into
+ /// \return next representable number
+ static half nexttoward(half from, long double to)
+ {
+ if(isnan(from))
+ return from;
+ long double lfrom = static_cast<long double>(from);
+ if(builtin_isnan(to) || lfrom == to)
+ return half(static_cast<float>(to));
+ if(!(from.data_&0x7FFF))
+ return half(binary, (static_cast<detail::uint16>(builtin_signbit(to))<<15)+1);
+ return half(binary, from.data_+(((from.data_>>15)^static_cast<unsigned>(lfrom<to))<<1)-1);
+ }
+
+ /// Sign implementation
+ /// \param x first operand
+ /// \param y second operand
+ /// \return composed value
+ static half copysign(half x, half y) { return half(binary, x.data_^((x.data_^y.data_)&0x8000)); }
+
+ /// Classification implementation.
+ /// \param arg value to classify
+ /// \retval true if infinite number
+ /// \retval false else
+ static int fpclassify(half arg)
+ {
+ unsigned int abs = arg.data_ & 0x7FFF;
+ return abs ? ((abs>0x3FF) ? ((abs>=0x7C00) ? ((abs>0x7C00) ? FP_NAN : FP_INFINITE) : FP_NORMAL) :FP_SUBNORMAL) : FP_ZERO;
+ }
+
+ /// Classification implementation.
+ /// \param arg value to classify
+ /// \retval true if finite number
+ /// \retval false else
+ static bool isfinite(half arg) { return (arg.data_&0x7C00) != 0x7C00; }
+
+ /// Classification implementation.
+ /// \param arg value to classify
+ /// \retval true if infinite number
+ /// \retval false else
+ static bool isinf(half arg) { return (arg.data_&0x7FFF) == 0x7C00; }
+
+ /// Classification implementation.
+ /// \param arg value to classify
+ /// \retval true if not a number
+ /// \retval false else
+ static bool isnan(half arg) { return (arg.data_&0x7FFF) > 0x7C00; }
+
+ /// Classification implementation.
+ /// \param arg value to classify
+ /// \retval true if normal number
+ /// \retval false else
+ static bool isnormal(half arg) { return ((arg.data_&0x7C00)!=0) & ((arg.data_&0x7C00)!=0x7C00); }
+
+ /// Sign bit implementation.
+ /// \param arg value to check
+ /// \retval true if signed
+ /// \retval false if unsigned
+ static bool signbit(half arg) { return (arg.data_&0x8000) != 0; }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if operands equal
+ /// \retval false else
+ static bool isequal(half x, half y) { return (x.data_==y.data_ || !((x.data_|y.data_)&0x7FFF)) && !isnan(x); }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if operands not equal
+ /// \retval false else
+ static bool isnotequal(half x, half y) { return (x.data_!=y.data_ && ((x.data_|y.data_)&0x7FFF)) || isnan(x); }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x > \a y
+ /// \retval false else
+ static bool isgreater(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ return xabs<=0x7C00 && yabs<=0x7C00 && (((xabs==x.data_) ? xabs : -xabs) > ((yabs==y.data_) ? yabs : -yabs));
+ }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x >= \a y
+ /// \retval false else
+ static bool isgreaterequal(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ return xabs<=0x7C00 && yabs<=0x7C00 && (((xabs==x.data_) ? xabs : -xabs) >= ((yabs==y.data_) ? yabs : -yabs));
+ }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x < \a y
+ /// \retval false else
+ static bool isless(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ return xabs<=0x7C00 && yabs<=0x7C00 && (((xabs==x.data_) ? xabs : -xabs) < ((yabs==y.data_) ? yabs : -yabs));
+ }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x <= \a y
+ /// \retval false else
+ static bool islessequal(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ return xabs<=0x7C00 && yabs<=0x7C00 && (((xabs==x.data_) ? xabs : -xabs) <= ((yabs==y.data_) ? yabs : -yabs));
+ }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if either \a x > \a y nor \a x < \a y
+ /// \retval false else
+ static bool islessgreater(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ if(xabs > 0x7C00 || yabs > 0x7C00)
+ return false;
+ int a = (xabs==x.data_) ? xabs : -xabs, b = (yabs==y.data_) ? yabs : -yabs;
+ return a < b || a > b;
+ }
+
+ /// Comparison implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if operand unordered
+ /// \retval false else
+ static bool isunordered(half x, half y) { return isnan(x) || isnan(y); }
+
+ private:
+ static double erf(double arg)
+ {
+ if(builtin_isinf(arg))
+ return (arg<0.0) ? -1.0 : 1.0;
+ double x2 = arg * arg, ax2 = 0.147 * x2, value = std::sqrt(1.0-std::exp(-x2*(1.2732395447351626861510701069801+ax2)/(1.0+ax2)));
+ return builtin_signbit(arg) ? -value : value;
+ }
+
+ static double lgamma(double arg)
+ {
+ double v = 1.0;
+ for(; arg<8.0; ++arg) v *= arg;
+ double w = 1.0 / (arg*arg);
+ return (((((((-0.02955065359477124183006535947712*w+0.00641025641025641025641025641026)*w+
+ -0.00191752691752691752691752691753)*w+8.4175084175084175084175084175084e-4)*w+
+ -5.952380952380952380952380952381e-4)*w+7.9365079365079365079365079365079e-4)*w+
+ -0.00277777777777777777777777777778)*w+0.08333333333333333333333333333333)/arg +
+ 0.91893853320467274178032973640562 - std::log(v) - arg + (arg-0.5) * std::log(arg);
+ }
+ };
+
+ /// Wrapper for unary half-precision functions needing specialization for individual argument types.
+ /// \tparam T argument type
+ template<typename T> struct unary_specialized
+ {
+ /// Negation implementation.
+ /// \param arg value to negate
+ /// \return negated value
+ static HALF_CONSTEXPR half negate(half arg) { return half(binary, arg.data_^0x8000); }
+
+ /// Absolute value implementation.
+ /// \param arg function argument
+ /// \return absolute value
+ static half fabs(half arg) { return half(binary, arg.data_&0x7FFF); }
+ };
+ template<> struct unary_specialized<expr>
+ {
+ static HALF_CONSTEXPR expr negate(float arg) { return expr(-arg); }
+ static expr fabs(float arg) { return expr(std::fabs(arg)); }
+ };
+
+ /// Wrapper for binary half-precision functions needing specialization for individual argument types.
+ /// \tparam T first argument type
+ /// \tparam U first argument type
+ template<typename T,typename U> struct binary_specialized
+ {
+ /// Minimum implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return minimum value
+ static expr fmin(float x, float y)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::fmin(x, y));
+ #else
+ if(builtin_isnan(x))
+ return expr(y);
+ if(builtin_isnan(y))
+ return expr(x);
+ return expr(std::min(x, y));
+ #endif
+ }
+
+ /// Maximum implementation.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return maximum value
+ static expr fmax(float x, float y)
+ {
+ #if HALF_ENABLE_CPP11_CMATH
+ return expr(std::fmax(x, y));
+ #else
+ if(builtin_isnan(x))
+ return expr(y);
+ if(builtin_isnan(y))
+ return expr(x);
+ return expr(std::max(x, y));
+ #endif
+ }
+ };
+ template<> struct binary_specialized<half,half>
+ {
+ static half fmin(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ if(xabs > 0x7C00)
+ return y;
+ if(yabs > 0x7C00)
+ return x;
+ return (((xabs==x.data_) ? xabs : -xabs) > ((yabs==y.data_) ? yabs : -yabs)) ? y : x;
+ }
+ static half fmax(half x, half y)
+ {
+ int xabs = x.data_ & 0x7FFF, yabs = y.data_ & 0x7FFF;
+ if(xabs > 0x7C00)
+ return y;
+ if(yabs > 0x7C00)
+ return x;
+ return (((xabs==x.data_) ? xabs : -xabs) < ((yabs==y.data_) ? yabs : -yabs)) ? y : x;
+ }
+ };
+
+ /// Helper class for half casts.
+ /// This class template has to be specialized for all valid cast argument to define an appropriate static `cast` member
+ /// function and a corresponding `type` member denoting its return type.
+ /// \tparam T destination type
+ /// \tparam U source type
+ /// \tparam R rounding mode to use
+ template<typename T,typename U,std::float_round_style R=(std::float_round_style)(HALF_ROUND_STYLE)> struct half_caster {};
+ template<typename U,std::float_round_style R> struct half_caster<half,U,R>
+ {
+ #if HALF_ENABLE_CPP11_STATIC_ASSERT && HALF_ENABLE_CPP11_TYPE_TRAITS
+ static_assert(std::is_arithmetic<U>::value, "half_cast from non-arithmetic type unsupported");
+ #endif
+
+ static half cast(U arg) { return cast_impl(arg, is_float<U>()); };
+
+ private:
+ static half cast_impl(U arg, true_type) { return half(binary, float2half<R>(arg)); }
+ static half cast_impl(U arg, false_type) { return half(binary, int2half<R>(arg)); }
+ };
+ template<typename T,std::float_round_style R> struct half_caster<T,half,R>
+ {
+ #if HALF_ENABLE_CPP11_STATIC_ASSERT && HALF_ENABLE_CPP11_TYPE_TRAITS
+ static_assert(std::is_arithmetic<T>::value, "half_cast to non-arithmetic type unsupported");
+ #endif
+
+ static T cast(half arg) { return cast_impl(arg, is_float<T>()); }
+
+ private:
+ static T cast_impl(half arg, true_type) { return half2float<T>(arg.data_); }
+ static T cast_impl(half arg, false_type) { return half2int<R,T>(arg.data_); }
+ };
+ template<typename T,std::float_round_style R> struct half_caster<T,expr,R>
+ {
+ #if HALF_ENABLE_CPP11_STATIC_ASSERT && HALF_ENABLE_CPP11_TYPE_TRAITS
+ static_assert(std::is_arithmetic<T>::value, "half_cast to non-arithmetic type unsupported");
+ #endif
+
+ static T cast(expr arg) { return cast_impl(arg, is_float<T>()); }
+
+ private:
+ static T cast_impl(float arg, true_type) { return static_cast<T>(arg); }
+ static T cast_impl(half arg, false_type) { return half2int<R,T>(arg.data_); }
+ };
+ template<std::float_round_style R> struct half_caster<half,half,R>
+ {
+ static half cast(half arg) { return arg; }
+ };
+ template<std::float_round_style R> struct half_caster<half,expr,R> : half_caster<half,half,R> {};
+
+ /// \name Comparison operators
+ /// \{
+
+ /// Comparison for equality.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if operands equal
+ /// \retval false else
+ template<typename T,typename U> typename enable<bool,T,U>::type operator==(T x, U y) { return functions::isequal(x, y); }
+
+ /// Comparison for inequality.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if operands not equal
+ /// \retval false else
+ template<typename T,typename U> typename enable<bool,T,U>::type operator!=(T x, U y) { return functions::isnotequal(x, y); }
+
+ /// Comparison for less than.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x less than \a y
+ /// \retval false else
+ template<typename T,typename U> typename enable<bool,T,U>::type operator<(T x, U y) { return functions::isless(x, y); }
+
+ /// Comparison for greater than.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x greater than \a y
+ /// \retval false else
+ template<typename T,typename U> typename enable<bool,T,U>::type operator>(T x, U y) { return functions::isgreater(x, y); }
+
+ /// Comparison for less equal.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x less equal \a y
+ /// \retval false else
+ template<typename T,typename U> typename enable<bool,T,U>::type operator<=(T x, U y) { return functions::islessequal(x, y); }
+
+ /// Comparison for greater equal.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x greater equal \a y
+ /// \retval false else
+ template<typename T,typename U> typename enable<bool,T,U>::type operator>=(T x, U y) { return functions::isgreaterequal(x, y); }
+
+ /// \}
+ /// \name Arithmetic operators
+ /// \{
+
+ /// Add halfs.
+ /// \param x left operand
+ /// \param y right operand
+ /// \return sum of half expressions
+ template<typename T,typename U> typename enable<expr,T,U>::type operator+(T x, U y) { return functions::plus(x, y); }
+
+ /// Subtract halfs.
+ /// \param x left operand
+ /// \param y right operand
+ /// \return difference of half expressions
+ template<typename T,typename U> typename enable<expr,T,U>::type operator-(T x, U y) { return functions::minus(x, y); }
+
+ /// Multiply halfs.
+ /// \param x left operand
+ /// \param y right operand
+ /// \return product of half expressions
+ template<typename T,typename U> typename enable<expr,T,U>::type operator*(T x, U y) { return functions::multiplies(x, y); }
+
+ /// Divide halfs.
+ /// \param x left operand
+ /// \param y right operand
+ /// \return quotient of half expressions
+ template<typename T,typename U> typename enable<expr,T,U>::type operator/(T x, U y) { return functions::divides(x, y); }
+
+ /// Identity.
+ /// \param arg operand
+ /// \return uncahnged operand
+ template<typename T> HALF_CONSTEXPR typename enable<T,T>::type operator+(T arg) { return arg; }
+
+ /// Negation.
+ /// \param arg operand
+ /// \return negated operand
+ template<typename T> HALF_CONSTEXPR typename enable<T,T>::type operator-(T arg) { return unary_specialized<T>::negate(arg); }
+
+ /// \}
+ /// \name Input and output
+ /// \{
+
+ /// Output operator.
+ /// \param out output stream to write into
+ /// \param arg half expression to write
+ /// \return reference to output stream
+ template<typename T,typename charT,typename traits> typename enable<std::basic_ostream<charT,traits>&,T>::type
+ operator<<(std::basic_ostream<charT,traits> &out, T arg) { return functions::write(out, arg); }
+
+ /// Input operator.
+ /// \param in input stream to read from
+ /// \param arg half to read into
+ /// \return reference to input stream
+ template<typename charT,typename traits> std::basic_istream<charT,traits>&
+ operator>>(std::basic_istream<charT,traits> &in, half &arg) { return functions::read(in, arg); }
+
+ /// \}
+ /// \name Basic mathematical operations
+ /// \{
+
+ /// Absolute value.
+ /// \param arg operand
+ /// \return absolute value of \a arg
+// template<typename T> typename enable<T,T>::type abs(T arg) { return unary_specialized<T>::fabs(arg); }
+ inline half abs(half arg) { return unary_specialized<half>::fabs(arg); }
+ inline expr abs(expr arg) { return unary_specialized<expr>::fabs(arg); }
+
+ /// Absolute value.
+ /// \param arg operand
+ /// \return absolute value of \a arg
+// template<typename T> typename enable<T,T>::type fabs(T arg) { return unary_specialized<T>::fabs(arg); }
+ inline half fabs(half arg) { return unary_specialized<half>::fabs(arg); }
+ inline expr fabs(expr arg) { return unary_specialized<expr>::fabs(arg); }
+
+ /// Remainder of division.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return remainder of floating point division.
+// template<typename T,typename U> typename enable<expr,T,U>::type fmod(T x, U y) { return functions::fmod(x, y); }
+ inline expr fmod(half x, half y) { return functions::fmod(x, y); }
+ inline expr fmod(half x, expr y) { return functions::fmod(x, y); }
+ inline expr fmod(expr x, half y) { return functions::fmod(x, y); }
+ inline expr fmod(expr x, expr y) { return functions::fmod(x, y); }
+
+ /// Remainder of division.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return remainder of floating point division.
+// template<typename T,typename U> typename enable<expr,T,U>::type remainder(T x, U y) { return functions::remainder(x, y); }
+ inline expr remainder(half x, half y) { return functions::remainder(x, y); }
+ inline expr remainder(half x, expr y) { return functions::remainder(x, y); }
+ inline expr remainder(expr x, half y) { return functions::remainder(x, y); }
+ inline expr remainder(expr x, expr y) { return functions::remainder(x, y); }
+
+ /// Remainder of division.
+ /// \param x first operand
+ /// \param y second operand
+ /// \param quo address to store some bits of quotient at
+ /// \return remainder of floating point division.
+// template<typename T,typename U> typename enable<expr,T,U>::type remquo(T x, U y, int *quo) { return functions::remquo(x, y, quo); }
+ inline expr remquo(half x, half y, int *quo) { return functions::remquo(x, y, quo); }
+ inline expr remquo(half x, expr y, int *quo) { return functions::remquo(x, y, quo); }
+ inline expr remquo(expr x, half y, int *quo) { return functions::remquo(x, y, quo); }
+ inline expr remquo(expr x, expr y, int *quo) { return functions::remquo(x, y, quo); }
+
+ /// Fused multiply add.
+ /// \param x first operand
+ /// \param y second operand
+ /// \param z third operand
+ /// \return ( \a x * \a y ) + \a z rounded as one operation.
+// template<typename T,typename U,typename V> typename enable<expr,T,U,V>::type fma(T x, U y, V z) { return functions::fma(x, y, z); }
+ inline expr fma(half x, half y, half z) { return functions::fma(x, y, z); }
+ inline expr fma(half x, half y, expr z) { return functions::fma(x, y, z); }
+ inline expr fma(half x, expr y, half z) { return functions::fma(x, y, z); }
+ inline expr fma(half x, expr y, expr z) { return functions::fma(x, y, z); }
+ inline expr fma(expr x, half y, half z) { return functions::fma(x, y, z); }
+ inline expr fma(expr x, half y, expr z) { return functions::fma(x, y, z); }
+ inline expr fma(expr x, expr y, half z) { return functions::fma(x, y, z); }
+ inline expr fma(expr x, expr y, expr z) { return functions::fma(x, y, z); }
+
+ /// Maximum of half expressions.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return maximum of operands
+// template<typename T,typename U> typename result<T,U>::type fmax(T x, U y) { return binary_specialized<T,U>::fmax(x, y); }
+ inline half fmax(half x, half y) { return binary_specialized<half,half>::fmax(x, y); }
+ inline expr fmax(half x, expr y) { return binary_specialized<half,expr>::fmax(x, y); }
+ inline expr fmax(expr x, half y) { return binary_specialized<expr,half>::fmax(x, y); }
+ inline expr fmax(expr x, expr y) { return binary_specialized<expr,expr>::fmax(x, y); }
+
+ /// Minimum of half expressions.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return minimum of operands
+// template<typename T,typename U> typename result<T,U>::type fmin(T x, U y) { return binary_specialized<T,U>::fmin(x, y); }
+ inline half fmin(half x, half y) { return binary_specialized<half,half>::fmin(x, y); }
+ inline expr fmin(half x, expr y) { return binary_specialized<half,expr>::fmin(x, y); }
+ inline expr fmin(expr x, half y) { return binary_specialized<expr,half>::fmin(x, y); }
+ inline expr fmin(expr x, expr y) { return binary_specialized<expr,expr>::fmin(x, y); }
+
+ /// Positive difference.
+ /// \param x first operand
+ /// \param y second operand
+ /// \return \a x - \a y or 0 if difference negative
+// template<typename T,typename U> typename enable<expr,T,U>::type fdim(T x, U y) { return functions::fdim(x, y); }
+ inline expr fdim(half x, half y) { return functions::fdim(x, y); }
+ inline expr fdim(half x, expr y) { return functions::fdim(x, y); }
+ inline expr fdim(expr x, half y) { return functions::fdim(x, y); }
+ inline expr fdim(expr x, expr y) { return functions::fdim(x, y); }
+
+ /// Get NaN value.
+ /// \return quiet NaN
+ inline half nanh(const char*) { return functions::nanh(); }
+
+ /// \}
+ /// \name Exponential functions
+ /// \{
+
+ /// Exponential function.
+ /// \param arg function argument
+ /// \return e raised to \a arg
+// template<typename T> typename enable<expr,T>::type exp(T arg) { return functions::exp(arg); }
+ inline expr exp(half arg) { return functions::exp(arg); }
+ inline expr exp(expr arg) { return functions::exp(arg); }
+
+ /// Exponential minus one.
+ /// \param arg function argument
+ /// \return e raised to \a arg subtracted by 1
+// template<typename T> typename enable<expr,T>::type expm1(T arg) { return functions::expm1(arg); }
+ inline expr expm1(half arg) { return functions::expm1(arg); }
+ inline expr expm1(expr arg) { return functions::expm1(arg); }
+
+ /// Binary exponential.
+ /// \param arg function argument
+ /// \return 2 raised to \a arg
+// template<typename T> typename enable<expr,T>::type exp2(T arg) { return functions::exp2(arg); }
+ inline expr exp2(half arg) { return functions::exp2(arg); }
+ inline expr exp2(expr arg) { return functions::exp2(arg); }
+
+ /// Natural logorithm.
+ /// \param arg function argument
+ /// \return logarithm of \a arg to base e
+// template<typename T> typename enable<expr,T>::type log(T arg) { return functions::log(arg); }
+ inline expr log(half arg) { return functions::log(arg); }
+ inline expr log(expr arg) { return functions::log(arg); }
+
+ /// Common logorithm.
+ /// \param arg function argument
+ /// \return logarithm of \a arg to base 10
+// template<typename T> typename enable<expr,T>::type log10(T arg) { return functions::log10(arg); }
+ inline expr log10(half arg) { return functions::log10(arg); }
+ inline expr log10(expr arg) { return functions::log10(arg); }
+
+ /// Natural logorithm.
+ /// \param arg function argument
+ /// \return logarithm of \a arg plus 1 to base e
+// template<typename T> typename enable<expr,T>::type log1p(T arg) { return functions::log1p(arg); }
+ inline expr log1p(half arg) { return functions::log1p(arg); }
+ inline expr log1p(expr arg) { return functions::log1p(arg); }
+
+ /// Binary logorithm.
+ /// \param arg function argument
+ /// \return logarithm of \a arg to base 2
+// template<typename T> typename enable<expr,T>::type log2(T arg) { return functions::log2(arg); }
+ inline expr log2(half arg) { return functions::log2(arg); }
+ inline expr log2(expr arg) { return functions::log2(arg); }
+
+ /// \}
+ /// \name Power functions
+ /// \{
+
+ /// Square root.
+ /// \param arg function argument
+ /// \return square root of \a arg
+// template<typename T> typename enable<expr,T>::type sqrt(T arg) { return functions::sqrt(arg); }
+ inline expr sqrt(half arg) { return functions::sqrt(arg); }
+ inline expr sqrt(expr arg) { return functions::sqrt(arg); }
+
+ /// Cubic root.
+ /// \param arg function argument
+ /// \return cubic root of \a arg
+// template<typename T> typename enable<expr,T>::type cbrt(T arg) { return functions::cbrt(arg); }
+ inline expr cbrt(half arg) { return functions::cbrt(arg); }
+ inline expr cbrt(expr arg) { return functions::cbrt(arg); }
+
+ /// Hypotenuse function.
+ /// \param x first argument
+ /// \param y second argument
+ /// \return square root of sum of squares without internal over- or underflows
+// template<typename T,typename U> typename enable<expr,T,U>::type hypot(T x, U y) { return functions::hypot(x, y); }
+ inline expr hypot(half x, half y) { return functions::hypot(x, y); }
+ inline expr hypot(half x, expr y) { return functions::hypot(x, y); }
+ inline expr hypot(expr x, half y) { return functions::hypot(x, y); }
+ inline expr hypot(expr x, expr y) { return functions::hypot(x, y); }
+
+ /// Power function.
+ /// \param base first argument
+ /// \param exp second argument
+ /// \return \a base raised to \a exp
+// template<typename T,typename U> typename enable<expr,T,U>::type pow(T base, U exp) { return functions::pow(base, exp); }
+ inline expr pow(half base, half exp) { return functions::pow(base, exp); }
+ inline expr pow(half base, expr exp) { return functions::pow(base, exp); }
+ inline expr pow(expr base, half exp) { return functions::pow(base, exp); }
+ inline expr pow(expr base, expr exp) { return functions::pow(base, exp); }
+
+ /// \}
+ /// \name Trigonometric functions
+ /// \{
+
+ /// Sine function.
+ /// \param arg function argument
+ /// \return sine value of \a arg
+// template<typename T> typename enable<expr,T>::type sin(T arg) { return functions::sin(arg); }
+ inline expr sin(half arg) { return functions::sin(arg); }
+ inline expr sin(expr arg) { return functions::sin(arg); }
+
+ /// Cosine function.
+ /// \param arg function argument
+ /// \return cosine value of \a arg
+// template<typename T> typename enable<expr,T>::type cos(T arg) { return functions::cos(arg); }
+ inline expr cos(half arg) { return functions::cos(arg); }
+ inline expr cos(expr arg) { return functions::cos(arg); }
+
+ /// Tangent function.
+ /// \param arg function argument
+ /// \return tangent value of \a arg
+// template<typename T> typename enable<expr,T>::type tan(T arg) { return functions::tan(arg); }
+ inline expr tan(half arg) { return functions::tan(arg); }
+ inline expr tan(expr arg) { return functions::tan(arg); }
+
+ /// Arc sine.
+ /// \param arg function argument
+ /// \return arc sine value of \a arg
+// template<typename T> typename enable<expr,T>::type asin(T arg) { return functions::asin(arg); }
+ inline expr asin(half arg) { return functions::asin(arg); }
+ inline expr asin(expr arg) { return functions::asin(arg); }
+
+ /// Arc cosine function.
+ /// \param arg function argument
+ /// \return arc cosine value of \a arg
+// template<typename T> typename enable<expr,T>::type acos(T arg) { return functions::acos(arg); }
+ inline expr acos(half arg) { return functions::acos(arg); }
+ inline expr acos(expr arg) { return functions::acos(arg); }
+
+ /// Arc tangent function.
+ /// \param arg function argument
+ /// \return arc tangent value of \a arg
+// template<typename T> typename enable<expr,T>::type atan(T arg) { return functions::atan(arg); }
+ inline expr atan(half arg) { return functions::atan(arg); }
+ inline expr atan(expr arg) { return functions::atan(arg); }
+
+ /// Arc tangent function.
+ /// \param x first argument
+ /// \param y second argument
+ /// \return arc tangent value
+// template<typename T,typename U> typename enable<expr,T,U>::type atan2(T x, U y) { return functions::atan2(x, y); }
+ inline expr atan2(half x, half y) { return functions::atan2(x, y); }
+ inline expr atan2(half x, expr y) { return functions::atan2(x, y); }
+ inline expr atan2(expr x, half y) { return functions::atan2(x, y); }
+ inline expr atan2(expr x, expr y) { return functions::atan2(x, y); }
+
+ /// \}
+ /// \name Hyperbolic functions
+ /// \{
+
+ /// Hyperbolic sine.
+ /// \param arg function argument
+ /// \return hyperbolic sine value of \a arg
+// template<typename T> typename enable<expr,T>::type sinh(T arg) { return functions::sinh(arg); }
+ inline expr sinh(half arg) { return functions::sinh(arg); }
+ inline expr sinh(expr arg) { return functions::sinh(arg); }
+
+ /// Hyperbolic cosine.
+ /// \param arg function argument
+ /// \return hyperbolic cosine value of \a arg
+// template<typename T> typename enable<expr,T>::type cosh(T arg) { return functions::cosh(arg); }
+ inline expr cosh(half arg) { return functions::cosh(arg); }
+ inline expr cosh(expr arg) { return functions::cosh(arg); }
+
+ /// Hyperbolic tangent.
+ /// \param arg function argument
+ /// \return hyperbolic tangent value of \a arg
+// template<typename T> typename enable<expr,T>::type tanh(T arg) { return functions::tanh(arg); }
+ inline expr tanh(half arg) { return functions::tanh(arg); }
+ inline expr tanh(expr arg) { return functions::tanh(arg); }
+
+ /// Hyperbolic area sine.
+ /// \param arg function argument
+ /// \return area sine value of \a arg
+// template<typename T> typename enable<expr,T>::type asinh(T arg) { return functions::asinh(arg); }
+ inline expr asinh(half arg) { return functions::asinh(arg); }
+ inline expr asinh(expr arg) { return functions::asinh(arg); }
+
+ /// Hyperbolic area cosine.
+ /// \param arg function argument
+ /// \return area cosine value of \a arg
+// template<typename T> typename enable<expr,T>::type acosh(T arg) { return functions::acosh(arg); }
+ inline expr acosh(half arg) { return functions::acosh(arg); }
+ inline expr acosh(expr arg) { return functions::acosh(arg); }
+
+ /// Hyperbolic area tangent.
+ /// \param arg function argument
+ /// \return area tangent value of \a arg
+// template<typename T> typename enable<expr,T>::type atanh(T arg) { return functions::atanh(arg); }
+ inline expr atanh(half arg) { return functions::atanh(arg); }
+ inline expr atanh(expr arg) { return functions::atanh(arg); }
+
+ /// \}
+ /// \name Error and gamma functions
+ /// \{
+
+ /// Error function.
+ /// \param arg function argument
+ /// \return error function value of \a arg
+// template<typename T> typename enable<expr,T>::type erf(T arg) { return functions::erf(arg); }
+ inline expr erf(half arg) { return functions::erf(arg); }
+ inline expr erf(expr arg) { return functions::erf(arg); }
+
+ /// Complementary error function.
+ /// \param arg function argument
+ /// \return 1 minus error function value of \a arg
+// template<typename T> typename enable<expr,T>::type erfc(T arg) { return functions::erfc(arg); }
+ inline expr erfc(half arg) { return functions::erfc(arg); }
+ inline expr erfc(expr arg) { return functions::erfc(arg); }
+
+ /// Natural logarithm of gamma function.
+ /// \param arg function argument
+ /// \return natural logarith of gamma function for \a arg
+// template<typename T> typename enable<expr,T>::type lgamma(T arg) { return functions::lgamma(arg); }
+ inline expr lgamma(half arg) { return functions::lgamma(arg); }
+ inline expr lgamma(expr arg) { return functions::lgamma(arg); }
+
+ /// Gamma function.
+ /// \param arg function argument
+ /// \return gamma function value of \a arg
+// template<typename T> typename enable<expr,T>::type tgamma(T arg) { return functions::tgamma(arg); }
+ inline expr tgamma(half arg) { return functions::tgamma(arg); }
+ inline expr tgamma(expr arg) { return functions::tgamma(arg); }
+
+ /// \}
+ /// \name Rounding
+ /// \{
+
+ /// Nearest integer not less than half value.
+ /// \param arg half to round
+ /// \return nearest integer not less than \a arg
+// template<typename T> typename enable<half,T>::type ceil(T arg) { return functions::ceil(arg); }
+ inline half ceil(half arg) { return functions::ceil(arg); }
+ inline half ceil(expr arg) { return functions::ceil(arg); }
+
+ /// Nearest integer not greater than half value.
+ /// \param arg half to round
+ /// \return nearest integer not greater than \a arg
+// template<typename T> typename enable<half,T>::type floor(T arg) { return functions::floor(arg); }
+ inline half floor(half arg) { return functions::floor(arg); }
+ inline half floor(expr arg) { return functions::floor(arg); }
+
+ /// Nearest integer not greater in magnitude than half value.
+ /// \param arg half to round
+ /// \return nearest integer not greater in magnitude than \a arg
+// template<typename T> typename enable<half,T>::type trunc(T arg) { return functions::trunc(arg); }
+ inline half trunc(half arg) { return functions::trunc(arg); }
+ inline half trunc(expr arg) { return functions::trunc(arg); }
+
+ /// Nearest integer.
+ /// \param arg half to round
+ /// \return nearest integer, rounded away from zero in half-way cases
+// template<typename T> typename enable<half,T>::type round(T arg) { return functions::round(arg); }
+ inline half round(half arg) { return functions::round(arg); }
+ inline half round(expr arg) { return functions::round(arg); }
+
+ /// Nearest integer.
+ /// \param arg half to round
+ /// \return nearest integer, rounded away from zero in half-way cases
+// template<typename T> typename enable<long,T>::type lround(T arg) { return functions::lround(arg); }
+ inline long lround(half arg) { return functions::lround(arg); }
+ inline long lround(expr arg) { return functions::lround(arg); }
+
+ /// Nearest integer using half's internal rounding mode.
+ /// \param arg half expression to round
+ /// \return nearest integer using default rounding mode
+// template<typename T> typename enable<half,T>::type nearbyint(T arg) { return functions::nearbyint(arg); }
+ inline half nearbyint(half arg) { return functions::rint(arg); }
+ inline half nearbyint(expr arg) { return functions::rint(arg); }
+
+ /// Nearest integer using half's internal rounding mode.
+ /// \param arg half expression to round
+ /// \return nearest integer using default rounding mode
+// template<typename T> typename enable<half,T>::type rint(T arg) { return functions::rint(arg); }
+ inline half rint(half arg) { return functions::rint(arg); }
+ inline half rint(expr arg) { return functions::rint(arg); }
+
+ /// Nearest integer using half's internal rounding mode.
+ /// \param arg half expression to round
+ /// \return nearest integer using default rounding mode
+// template<typename T> typename enable<long,T>::type lrint(T arg) { return functions::lrint(arg); }
+ inline long lrint(half arg) { return functions::lrint(arg); }
+ inline long lrint(expr arg) { return functions::lrint(arg); }
+ #if HALF_ENABLE_CPP11_LONG_LONG
+ /// Nearest integer.
+ /// \param arg half to round
+ /// \return nearest integer, rounded away from zero in half-way cases
+// template<typename T> typename enable<long long,T>::type llround(T arg) { return functions::llround(arg); }
+ inline long long llround(half arg) { return functions::llround(arg); }
+ inline long long llround(expr arg) { return functions::llround(arg); }
+
+ /// Nearest integer using half's internal rounding mode.
+ /// \param arg half expression to round
+ /// \return nearest integer using default rounding mode
+// template<typename T> typename enable<long long,T>::type llrint(T arg) { return functions::llrint(arg); }
+ inline long long llrint(half arg) { return functions::llrint(arg); }
+ inline long long llrint(expr arg) { return functions::llrint(arg); }
+ #endif
+
+ /// \}
+ /// \name Floating point manipulation
+ /// \{
+
+ /// Decompress floating point number.
+ /// \param arg number to decompress
+ /// \param exp address to store exponent at
+ /// \return significant in range [0.5, 1)
+// template<typename T> typename enable<half,T>::type frexp(T arg, int *exp) { return functions::frexp(arg, exp); }
+ inline half frexp(half arg, int *exp) { return functions::frexp(arg, exp); }
+ inline half frexp(expr arg, int *exp) { return functions::frexp(arg, exp); }
+
+ /// Multiply by power of two.
+ /// \param arg number to modify
+ /// \param exp power of two to multiply with
+ /// \return \a arg multplied by 2 raised to \a exp
+// template<typename T> typename enable<half,T>::type ldexp(T arg, int exp) { return functions::scalbln(arg, exp); }
+ inline half ldexp(half arg, int exp) { return functions::scalbln(arg, exp); }
+ inline half ldexp(expr arg, int exp) { return functions::scalbln(arg, exp); }
+
+ /// Extract integer and fractional parts.
+ /// \param arg number to decompress
+ /// \param iptr address to store integer part at
+ /// \return fractional part
+// template<typename T> typename enable<half,T>::type modf(T arg, half *iptr) { return functions::modf(arg, iptr); }
+ inline half modf(half arg, half *iptr) { return functions::modf(arg, iptr); }
+ inline half modf(expr arg, half *iptr) { return functions::modf(arg, iptr); }
+
+ /// Multiply by power of two.
+ /// \param arg number to modify
+ /// \param exp power of two to multiply with
+ /// \return \a arg multplied by 2 raised to \a exp
+// template<typename T> typename enable<half,T>::type scalbn(T arg, int exp) { return functions::scalbln(arg, exp); }
+ inline half scalbn(half arg, int exp) { return functions::scalbln(arg, exp); }
+ inline half scalbn(expr arg, int exp) { return functions::scalbln(arg, exp); }
+
+ /// Multiply by power of two.
+ /// \param arg number to modify
+ /// \param exp power of two to multiply with
+ /// \return \a arg multplied by 2 raised to \a exp
+// template<typename T> typename enable<half,T>::type scalbln(T arg, long exp) { return functions::scalbln(arg, exp); }
+ inline half scalbln(half arg, long exp) { return functions::scalbln(arg, exp); }
+ inline half scalbln(expr arg, long exp) { return functions::scalbln(arg, exp); }
+
+ /// Extract exponent.
+ /// \param arg number to query
+ /// \return floating point exponent
+ /// \retval FP_ILOGB0 for zero
+ /// \retval FP_ILOGBNAN for NaN
+ /// \retval MAX_INT for infinity
+// template<typename T> typename enable<int,T>::type ilogb(T arg) { return functions::ilogb(arg); }
+ inline int ilogb(half arg) { return functions::ilogb(arg); }
+ inline int ilogb(expr arg) { return functions::ilogb(arg); }
+
+ /// Extract exponent.
+ /// \param arg number to query
+ /// \return floating point exponent
+// template<typename T> typename enable<half,T>::type logb(T arg) { return functions::logb(arg); }
+ inline half logb(half arg) { return functions::logb(arg); }
+ inline half logb(expr arg) { return functions::logb(arg); }
+
+ /// Next representable value.
+ /// \param from value to compute next representable value for
+ /// \param to direction towards which to compute next value
+ /// \return next representable value after \a from in direction towards \a to
+// template<typename T,typename U> typename enable<half,T,U>::type nextafter(T from, U to) { return functions::nextafter(from, to); }
+ inline half nextafter(half from, half to) { return functions::nextafter(from, to); }
+ inline half nextafter(half from, expr to) { return functions::nextafter(from, to); }
+ inline half nextafter(expr from, half to) { return functions::nextafter(from, to); }
+ inline half nextafter(expr from, expr to) { return functions::nextafter(from, to); }
+
+ /// Next representable value.
+ /// \param from value to compute next representable value for
+ /// \param to direction towards which to compute next value
+ /// \return next representable value after \a from in direction towards \a to
+// template<typename T> typename enable<half,T>::type nexttoward(T from, long double to) { return functions::nexttoward(from, to); }
+ inline half nexttoward(half from, long double to) { return functions::nexttoward(from, to); }
+ inline half nexttoward(expr from, long double to) { return functions::nexttoward(from, to); }
+
+ /// Take sign.
+ /// \param x value to change sign for
+ /// \param y value to take sign from
+ /// \return value equal to \a x in magnitude and to \a y in sign
+// template<typename T,typename U> typename enable<half,T,U>::type copysign(T x, U y) { return functions::copysign(x, y); }
+ inline half copysign(half x, half y) { return functions::copysign(x, y); }
+ inline half copysign(half x, expr y) { return functions::copysign(x, y); }
+ inline half copysign(expr x, half y) { return functions::copysign(x, y); }
+ inline half copysign(expr x, expr y) { return functions::copysign(x, y); }
+
+ /// \}
+ /// \name Floating point classification
+ /// \{
+
+
+ /// Classify floating point value.
+ /// \param arg number to classify
+ /// \retval FP_ZERO for positive and negative zero
+ /// \retval FP_SUBNORMAL for subnormal numbers
+ /// \retval FP_INFINITY for positive and negative infinity
+ /// \retval FP_NAN for NaNs
+ /// \retval FP_NORMAL for all other (normal) values
+// template<typename T> typename enable<int,T>::type fpclassify(T arg) { return functions::fpclassify(arg); }
+ inline int fpclassify(half arg) { return functions::fpclassify(arg); }
+ inline int fpclassify(expr arg) { return functions::fpclassify(arg); }
+
+ /// Check if finite number.
+ /// \param arg number to check
+ /// \retval true if neither infinity nor NaN
+ /// \retval false else
+// template<typename T> typename enable<bool,T>::type isfinite(T arg) { return functions::isfinite(arg); }
+ inline bool isfinite(half arg) { return functions::isfinite(arg); }
+ inline bool isfinite(expr arg) { return functions::isfinite(arg); }
+
+ /// Check for infinity.
+ /// \param arg number to check
+ /// \retval true for positive or negative infinity
+ /// \retval false else
+// template<typename T> typename enable<bool,T>::type isinf(T arg) { return functions::isinf(arg); }
+ inline bool isinf(half arg) { return functions::isinf(arg); }
+ inline bool isinf(expr arg) { return functions::isinf(arg); }
+
+ /// Check for NaN.
+ /// \param arg number to check
+ /// \retval true for NaNs
+ /// \retval false else
+// template<typename T> typename enable<bool,T>::type isnan(T arg) { return functions::isnan(arg); }
+ inline bool isnan(half arg) { return functions::isnan(arg); }
+ inline bool isnan(expr arg) { return functions::isnan(arg); }
+
+ /// Check if normal number.
+ /// \param arg number to check
+ /// \retval true if normal number
+ /// \retval false if either subnormal, zero, infinity or NaN
+// template<typename T> typename enable<bool,T>::type isnormal(T arg) { return functions::isnormal(arg); }
+ inline bool isnormal(half arg) { return functions::isnormal(arg); }
+ inline bool isnormal(expr arg) { return functions::isnormal(arg); }
+
+ /// Check sign.
+ /// \param arg number to check
+ /// \retval true for negative number
+ /// \retval false for positive number
+// template<typename T> typename enable<bool,T>::type signbit(T arg) { return functions::signbit(arg); }
+ inline bool signbit(half arg) { return functions::signbit(arg); }
+ inline bool signbit(expr arg) { return functions::signbit(arg); }
+
+ /// \}
+ /// \name Comparison
+ /// \{
+
+ /// Comparison for greater than.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x greater than \a y
+ /// \retval false else
+// template<typename T,typename U> typename enable<bool,T,U>::type isgreater(T x, U y) { return functions::isgreater(x, y); }
+ inline bool isgreater(half x, half y) { return functions::isgreater(x, y); }
+ inline bool isgreater(half x, expr y) { return functions::isgreater(x, y); }
+ inline bool isgreater(expr x, half y) { return functions::isgreater(x, y); }
+ inline bool isgreater(expr x, expr y) { return functions::isgreater(x, y); }
+
+ /// Comparison for greater equal.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x greater equal \a y
+ /// \retval false else
+// template<typename T,typename U> typename enable<bool,T,U>::type isgreaterequal(T x, U y) { return functions::isgreaterequal(x, y); }
+ inline bool isgreaterequal(half x, half y) { return functions::isgreaterequal(x, y); }
+ inline bool isgreaterequal(half x, expr y) { return functions::isgreaterequal(x, y); }
+ inline bool isgreaterequal(expr x, half y) { return functions::isgreaterequal(x, y); }
+ inline bool isgreaterequal(expr x, expr y) { return functions::isgreaterequal(x, y); }
+
+ /// Comparison for less than.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x less than \a y
+ /// \retval false else
+// template<typename T,typename U> typename enable<bool,T,U>::type isless(T x, U y) { return functions::isless(x, y); }
+ inline bool isless(half x, half y) { return functions::isless(x, y); }
+ inline bool isless(half x, expr y) { return functions::isless(x, y); }
+ inline bool isless(expr x, half y) { return functions::isless(x, y); }
+ inline bool isless(expr x, expr y) { return functions::isless(x, y); }
+
+ /// Comparison for less equal.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if \a x less equal \a y
+ /// \retval false else
+// template<typename T,typename U> typename enable<bool,T,U>::type islessequal(T x, U y) { return functions::islessequal(x, y); }
+ inline bool islessequal(half x, half y) { return functions::islessequal(x, y); }
+ inline bool islessequal(half x, expr y) { return functions::islessequal(x, y); }
+ inline bool islessequal(expr x, half y) { return functions::islessequal(x, y); }
+ inline bool islessequal(expr x, expr y) { return functions::islessequal(x, y); }
+
+ /// Comarison for less or greater.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if either less or greater
+ /// \retval false else
+// template<typename T,typename U> typename enable<bool,T,U>::type islessgreater(T x, U y) { return functions::islessgreater(x, y); }
+ inline bool islessgreater(half x, half y) { return functions::islessgreater(x, y); }
+ inline bool islessgreater(half x, expr y) { return functions::islessgreater(x, y); }
+ inline bool islessgreater(expr x, half y) { return functions::islessgreater(x, y); }
+ inline bool islessgreater(expr x, expr y) { return functions::islessgreater(x, y); }
+
+ /// Check if unordered.
+ /// \param x first operand
+ /// \param y second operand
+ /// \retval true if unordered (one or two NaN operands)
+ /// \retval false else
+// template<typename T,typename U> typename enable<bool,T,U>::type isunordered(T x, U y) { return functions::isunordered(x, y); }
+ inline bool isunordered(half x, half y) { return functions::isunordered(x, y); }
+ inline bool isunordered(half x, expr y) { return functions::isunordered(x, y); }
+ inline bool isunordered(expr x, half y) { return functions::isunordered(x, y); }
+ inline bool isunordered(expr x, expr y) { return functions::isunordered(x, y); }
+
+ /// \name Casting
+ /// \{
+
+ /// Cast to or from half-precision floating point number.
+ /// This casts between [half](\ref half_float::half) and any built-in arithmetic type. The values are converted
+ /// directly using the given rounding mode, without any roundtrip over `float` that a `static_cast` would otherwise do.
+ /// It uses the default rounding mode.
+ ///
+ /// Using this cast with neither of the two types being a [half](\ref half_float::half) or with any of the two types
+ /// not being a built-in arithmetic type (apart from [half](\ref half_float::half), of course) results in a compiler
+ /// error and casting between [half](\ref half_float::half)s is just a no-op.
+ /// \tparam T destination type (half or built-in arithmetic type)
+ /// \tparam U source type (half or built-in arithmetic type)
+ /// \param arg value to cast
+ /// \return \a arg converted to destination type
+ template<typename T,typename U> T half_cast(U arg) { return half_caster<T,U>::cast(arg); }
+
+ /// Cast to or from half-precision floating point number.
+ /// This casts between [half](\ref half_float::half) and any built-in arithmetic type. The values are converted
+ /// directly using the given rounding mode, without any roundtrip over `float` that a `static_cast` would otherwise do.
+ ///
+ /// Using this cast with neither of the two types being a [half](\ref half_float::half) or with any of the two types
+ /// not being a built-in arithmetic type (apart from [half](\ref half_float::half), of course) results in a compiler
+ /// error and casting between [half](\ref half_float::half)s is just a no-op.
+ /// \tparam T destination type (half or built-in arithmetic type)
+ /// \tparam R rounding mode to use.
+ /// \tparam U source type (half or built-in arithmetic type)
+ /// \param arg value to cast
+ /// \return \a arg converted to destination type
+ template<typename T,std::float_round_style R,typename U> T half_cast(U arg) { return half_caster<T,U,R>::cast(arg); }
+ /// \}
+ }
+
+ using detail::operator==;
+ using detail::operator!=;
+ using detail::operator<;
+ using detail::operator>;
+ using detail::operator<=;
+ using detail::operator>=;
+ using detail::operator+;
+ using detail::operator-;
+ using detail::operator*;
+ using detail::operator/;
+ using detail::operator<<;
+ using detail::operator>>;
+
+ using detail::abs;
+ using detail::fabs;
+ using detail::fmod;
+ using detail::remainder;
+ using detail::remquo;
+ using detail::fma;
+ using detail::fmax;
+ using detail::fmin;
+ using detail::fdim;
+ using detail::nanh;
+ using detail::exp;
+ using detail::expm1;
+ using detail::exp2;
+ using detail::log;
+ using detail::log10;
+ using detail::log1p;
+ using detail::log2;
+ using detail::sqrt;
+ using detail::cbrt;
+ using detail::hypot;
+ using detail::pow;
+ using detail::sin;
+ using detail::cos;
+ using detail::tan;
+ using detail::asin;
+ using detail::acos;
+ using detail::atan;
+ using detail::atan2;
+ using detail::sinh;
+ using detail::cosh;
+ using detail::tanh;
+ using detail::asinh;
+ using detail::acosh;
+ using detail::atanh;
+ using detail::erf;
+ using detail::erfc;
+ using detail::lgamma;
+ using detail::tgamma;
+ using detail::ceil;
+ using detail::floor;
+ using detail::trunc;
+ using detail::round;
+ using detail::lround;
+ using detail::nearbyint;
+ using detail::rint;
+ using detail::lrint;
+#if HALF_ENABLE_CPP11_LONG_LONG
+ using detail::llround;
+ using detail::llrint;
+#endif
+ using detail::frexp;
+ using detail::ldexp;
+ using detail::modf;
+ using detail::scalbn;
+ using detail::scalbln;
+ using detail::ilogb;
+ using detail::logb;
+ using detail::nextafter;
+ using detail::nexttoward;
+ using detail::copysign;
+ using detail::fpclassify;
+ using detail::isfinite;
+ using detail::isinf;
+ using detail::isnan;
+ using detail::isnormal;
+ using detail::signbit;
+ using detail::isgreater;
+ using detail::isgreaterequal;
+ using detail::isless;
+ using detail::islessequal;
+ using detail::islessgreater;
+ using detail::isunordered;
+
+ using detail::half_cast;
+}
+
+
+/// Extensions to the C++ standard library.
+namespace std
+{
+ /// Numeric limits for half-precision floats.
+ /// Because of the underlying single-precision implementation of many operations, it inherits some properties from
+ /// `std::numeric_limits<float>`.
+ template<> class numeric_limits<half_float::half> : public numeric_limits<float>
+ {
+ public:
+ /// Supports signed values.
+ static HALF_CONSTEXPR_CONST bool is_signed = true;
+
+ /// Is not exact.
+ static HALF_CONSTEXPR_CONST bool is_exact = false;
+
+ /// Doesn't provide modulo arithmetic.
+ static HALF_CONSTEXPR_CONST bool is_modulo = false;
+
+ /// IEEE conformant.
+ static HALF_CONSTEXPR_CONST bool is_iec559 = true;
+
+ /// Supports infinity.
+ static HALF_CONSTEXPR_CONST bool has_infinity = true;
+
+ /// Supports quiet NaNs.
+ static HALF_CONSTEXPR_CONST bool has_quiet_NaN = true;
+
+ /// Supports subnormal values.
+ static HALF_CONSTEXPR_CONST float_denorm_style has_denorm = denorm_present;
+
+ /// Rounding mode.
+ /// Due to the mix of internal single-precision computations (using the rounding mode of the underlying
+ /// single-precision implementation) with the rounding mode of the single-to-half conversions, the actual rounding
+ /// mode might be `std::round_indeterminate` if the default half-precision rounding mode doesn't match the
+ /// single-precision rounding mode.
+ static HALF_CONSTEXPR_CONST float_round_style round_style = (std::numeric_limits<float>::round_style==
+ half_float::half::round_style) ? half_float::half::round_style : round_indeterminate;
+
+ /// Significant digits.
+ static HALF_CONSTEXPR_CONST int digits = 11;
+
+ /// Significant decimal digits.
+ static HALF_CONSTEXPR_CONST int digits10 = 3;
+
+ /// Required decimal digits to represent all possible values.
+ static HALF_CONSTEXPR_CONST int max_digits10 = 5;
+
+ /// Number base.
+ static HALF_CONSTEXPR_CONST int radix = 2;
+
+ /// One more than smallest exponent.
+ static HALF_CONSTEXPR_CONST int min_exponent = -13;
+
+ /// Smallest normalized representable power of 10.
+ static HALF_CONSTEXPR_CONST int min_exponent10 = -4;
+
+ /// One more than largest exponent
+ static HALF_CONSTEXPR_CONST int max_exponent = 16;
+
+ /// Largest finitely representable power of 10.
+ static HALF_CONSTEXPR_CONST int max_exponent10 = 4;
+
+ /// Smallest positive normal value.
+ static HALF_CONSTEXPR half_float::half min() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x0400); }
+
+ /// Smallest finite value.
+ static HALF_CONSTEXPR half_float::half lowest() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0xFBFF); }
+
+ /// Largest finite value.
+ static HALF_CONSTEXPR half_float::half max() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x7BFF); }
+
+ /// Difference between one and next representable value.
+ static HALF_CONSTEXPR half_float::half epsilon() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x1400); }
+
+ /// Maximum rounding error.
+ static HALF_CONSTEXPR half_float::half round_error() HALF_NOTHROW
+ { return half_float::half(half_float::detail::binary, (round_style==std::round_to_nearest) ? 0x3800 : 0x3C00); }
+
+ /// Positive infinity.
+ static HALF_CONSTEXPR half_float::half infinity() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x7C00); }
+
+ /// Quiet NaN.
+ static HALF_CONSTEXPR half_float::half quiet_NaN() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x7FFF); }
+
+ /// Signalling NaN.
+ static HALF_CONSTEXPR half_float::half signaling_NaN() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x7DFF); }
+
+ /// Smallest positive subnormal value.
+ static HALF_CONSTEXPR half_float::half denorm_min() HALF_NOTHROW { return half_float::half(half_float::detail::binary, 0x0001); }
+ };
+
+#if HALF_ENABLE_CPP11_HASH
+ /// Hash function for half-precision floats.
+ /// This is only defined if C++11 `std::hash` is supported and enabled.
+ template<> struct hash<half_float::half> //: unary_function<half_float::half,size_t>
+ {
+ /// Type of function argument.
+ typedef half_float::half argument_type;
+
+ /// Function return type.
+ typedef size_t result_type;
+
+ /// Compute hash function.
+ /// \param arg half to hash
+ /// \return hash value
+ result_type operator()(argument_type arg) const
+ { return hash<half_float::detail::uint16>()(static_cast<unsigned>(arg.data_)&-(arg.data_!=0x8000)); }
+ };
+#endif
+}
+
+
+#undef HALF_CONSTEXPR
+#undef HALF_CONSTEXPR_CONST
+#undef HALF_NOEXCEPT
+#undef HALF_NOTHROW
+#ifdef HALF_POP_WARNINGS
+ #pragma warning(pop)
+ #undef HALF_POP_WARNINGS
+#endif
+
+#endif
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 16f33c6..edca5b9 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -25,7 +25,7 @@ // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - +#include "half.hpp" #include "instructions.h" #include "ptx_ir.h" #include "opcodes.h" @@ -45,6 +45,7 @@ #include "cuda_device_runtime.h" #include <stdarg.h> +using half_float::half; unsigned ptx_instruction::g_num_ptx_inst_uid=0; @@ -1549,10 +1550,11 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) offset=8*(thrd%2); thread = core->get_thread_info()[tid+thrd]; printf("thread=%d:",thrd); - for(i=8;i<=31;i++){ + //for(i=8;i<=31;i++){ + for(i=0;i<=0;i++){ const operand_info &src_a= pI->operand_lookup(i); src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); - printf("%f ",src_data.f32); + printf("%x ",src_data.f16); if(i<=15) matrix_a[row][offset+(i)%8]=src_data; else if((i>15)&&(i<=23)) @@ -1568,27 +1570,27 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) printf("MATRIX_A\n"); for (i=0;i<16;i++){ for(j=0;j<16;j++){ - printf("%f ",matrix_a[i][j].f32); + printf("%x ",matrix_a[i][j].f16); } printf("\n"); } printf("MATRIX_B\n"); for (i=0;i<16;i++){ for(j=0;j<16;j++){ - printf("%f ",matrix_b[i][j].f32); + printf("%x ",matrix_b[i][j].f16); } printf("\n"); } printf("MATRIX_C\n"); for (i=0;i<16;i++){ for(j=0;j<16;j++){ - printf("%f ",matrix_c[i][j].f32); + printf("%x ",matrix_c[i][j].f16); } printf("\n"); } for (i=0;i<16;i++){ for(j=0;j<16;j++){ - matrix_d[i][j].f32=0; + matrix_d[i][j].f16=0; } } @@ -1860,6 +1862,8 @@ unsigned int saturatei(unsigned int a, unsigned int max) ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) { + half mytemp; + float myfloat; assert( from_width == 32); enum cuda_math::cudaRoundMode mode = cuda_math::cudaRoundZero; @@ -1903,7 +1907,11 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, } else { switch ( to_width ) { case 16: //assert(0); break; - y.f16 = x.f32; + mytemp=half(x.f32); + myfloat=mytemp; + y.f16 =mytemp; + //y.f16 = half(x.f32); + printf("f2x: %f\n",myfloat); break; case 32: assert(0); break; // handled by f2f case 64: @@ -2621,45 +2629,51 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { + size_t size; + int t; const operand_info &dst = pI->dst(); const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); unsigned type = pI->get_type(); - int tid = inst.warp_id_func() * core->get_warp_size(); - int thrd; + int tid = inst.warp_id_func()*core->get_warp_size(); + int thrd,odd,inx; ptx_thread_info *thread; - thread = core->get_thread_info()[tid]; + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + thread = core->get_thread_info()[tid+thrd]; + odd=thrd%2; + inx=thrd/2; + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + ptx_reg_t src2_data = thread->get_operand_value(src2, dst, type, thread, 1); - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + ptx_reg_t data; + memory_space_t space = pI->get_space(); - ptx_reg_t data; - memory_space_t space = pI->get_space(); + memory_space *mem = NULL; + addr_t addr = src1_data.u32; - memory_space *mem = NULL; - addr_t addr = src1_data.u32; + decode_space(space,thread,src1,mem,addr); - decode_space(space,thread,src1,mem,addr); + data.u64=0; + type_info_key::type_decode(type,size,t); + ptx_reg_t data1, data2, data3, data4; + ptx_reg_t data5, data6, data7, data8; + printf("mma_ld: thrd=%d,addr=%d, fp16(size=%d), stride=%d\n",thrd,src1_data.u32,size,src2_data.u32); + mem->read(addr+inx*2*src2_data.u32+odd*16,size/8,&data1.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+size/8,size/8,&data2.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+2*size/8,size/8,&data3.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+3*size/8,size/8,&data4.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+4*size/8,size/8,&data5.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+5*size/8,size/8,&data6.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+6*size/8,size/8,&data7.s64); + mem->read(addr+inx*2*src2_data.u32+odd*16+7*size/8,size/8,&data8.s64); + thread->set_wmma_vector_operand_values(dst,data1,data2,data3,data4,data5,data6,data7,data8); + printf("thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",0,data1.s64,data2.s64,data3.s64,data4.s64,data5.s64,data6.s64,data7.s64,data8.s64); - size_t size; - int t; - data.u64=0; - type_info_key::type_decode(type,size,t); - ptx_reg_t data1, data2, data3, data4; - ptx_reg_t data5, data6, data7, data8; - mem->read(addr,size/8,&data1.s64); - mem->read(addr+size/8,size/8,&data2.s64); - mem->read(addr+2*size/8,size/8,&data3.s64); - mem->read(addr+3*size/8,size/8,&data4.s64); - mem->read(addr+4*size/8,size/8,&data5.s64); - mem->read(addr+5*size/8,size/8,&data6.s64); - mem->read(addr+6*size/8,size/8,&data7.s64); - mem->read(addr+7*size/8,size/8,&data8.s64); - thread->set_wmma_vector_operand_values(dst,data1,data2,data3,data4,data5,data6,data7,data8); - - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; + } } void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -4190,7 +4204,7 @@ void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if (!vector_spec) { data = thread->get_operand_value(src1, dst, type, thread, 1); mem->write(addr,size/8,&data.s64,thread,pI); - printf("addr=%d data=%d\n",addr,data.s64); + printf("st:addr=%x data=%x\n",addr,data.s64); } else { if (vector_spec == V2_TYPE) { ptx_reg_t* ptx_regs = new ptx_reg_t[2]; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 403ce5b..fbd7881 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -28,7 +28,7 @@ #define ptx_sim_h_INCLUDED #include <stdlib.h> - +#include "half.hpp" #include "../abstract_hardware_model.h" #include "../tr1_hash_map.h" @@ -53,6 +53,8 @@ struct param_t { #include "memory.h" +using half_float::half; + union ptx_reg_t { ptx_reg_t() { bits.ms = 0; @@ -126,7 +128,7 @@ union ptx_reg_t { unsigned short u16; unsigned int u32; unsigned long long u64; - float f16; + half f16; float f32; double f64; struct { |