diff options
| author | Timothy G Rogers <[email protected]> | 2018-10-11 14:16:33 -0400 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2018-10-11 14:16:33 -0400 |
| commit | 982d7e02ff64c8978d5635bbc2b3515e2145574b (patch) | |
| tree | 04e71c63714464d17105f8ae2563a99365d821f8 /configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | |
| parent | a43799f779a2cf23728659733649506a2d5420df (diff) | |
| parent | beeafb66d2e2bb441ab1eacade75322a72961be0 (diff) | |
Merge pull request #28 from abdallm/dev-purdue-integration
Dev purdue integration
Diffstat (limited to 'configs/4.x-cfgs/SM6_TITANX/gpgpusim.config')
| -rw-r--r-- | configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config index 45a87cd..1b4e6e3 100644 --- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -71,21 +71,25 @@ -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 +# By default, L1 cache is disabled in Pascal P102. +# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 -gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 -l1_latency 82 -smem_latency 24 +-gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 0 +-perf_sim_memcpy 1 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 |