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authorMahmoud <[email protected]>2018-10-09 12:07:25 -0400
committerMahmoud <[email protected]>2018-10-09 12:07:25 -0400
commitfdbb4aef32a36ff625612c82c58039699af2b23b (patch)
tree9981fab8201f5141ec81f735c3737e7b7b04673f /configs/4.x-cfgs/SM6_TITANX
parentadc215c1e16ce6515b82bc7596f3448bd7817804 (diff)
flushing L1 cache
Diffstat (limited to 'configs/4.x-cfgs/SM6_TITANX')
-rw-r--r--configs/4.x-cfgs/SM6_TITANX/gpgpusim.config1
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 45a87cd..3723163 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -76,6 +76,7 @@
-gpgpu_n_cluster_ejection_buffer_size 32
-l1_latency 82
-smem_latency 24
+-gpgpu_flush_l1_cache 1
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32