diff options
| author | Wilson Fung <[email protected]> | 2012-06-18 21:59:31 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:47:32 -0700 |
| commit | dad9e2a5cfb0f1f49279a6d2746454dd32f6eb85 (patch) | |
| tree | 46a717e2bbba89b90ae5c737aae7caeb7e4b4bcd /configs/Fermi | |
| parent | 46716354407900581e86fa3537ce156f45d340ae (diff) | |
Fixed GDDR5 parameters in Fermi config:
- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
- Decreased the DRAM clock to 924MHz from 1848MHz.
- Corrected CAS Latency and Write Latency in the timing constraints.
- Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
Diffstat (limited to 'configs/Fermi')
| -rw-r--r-- | configs/Fermi/gpgpusim.config | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config index 1a63db1..1122bbe 100644 --- a/configs/Fermi/gpgpusim.config +++ b/configs/Fermi/gpgpusim.config @@ -12,7 +12,7 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:1400.0:700.0:1848.0 +-gpgpu_clock_domains 700.0:1400.0:700.0:924.0 # shader core pipeline config -gpgpu_shader_registers 32768 @@ -75,14 +75,17 @@ # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBBCCCC.CCSSSSSS # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 # {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12:4:3:2 +# -gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:CL=12: +# WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2 +-gpgpu_dram_timing_opt 16:2:6:12:28:12:40:12:4:5:12:4:3:2 # GDDR3 #-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11 |