diff options
| author | Tayler Hetherington <[email protected]> | 2014-07-08 16:06:37 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:50:59 -0700 |
| commit | 94a6b6c513c0afaf86770d2af0e41c8d7d0da3f5 (patch) | |
| tree | de4bb179535247ce61f018655ead524d90926c52 /configs/GTX480 | |
| parent | 7cfef9166fe19e7fe73bf0d71e114dfec56e011b (diff) | |
- Code review 1173001
- Added a parameter to the cache configuration to configure the set index function.
- Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
Diffstat (limited to 'configs/GTX480')
| -rw-r--r-- | configs/GTX480/gpgpusim.config | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index b0035a5..436cb41 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -45,22 +45,23 @@ # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo --gpgpu_cache:dl1 32:128:4,L:L:m:N,A:32:8,8 +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 -gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 64:128:6,L:L:m:N,A:32:8,8 +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W,A:32:4,4:0,32 +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 --gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4 +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 # enable operand collector -gpgpu_operand_collector_num_units_sp 6 |