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authortgrogers <[email protected]>2018-03-25 16:51:21 -0400
committertgrogers <[email protected]>2018-03-25 16:51:21 -0400
commit4e91a60a48b07f41f4bfb4d59fa2355024a3914b (patch)
tree331aefc5a9df52299b7e0f9d8de56439cf187d36 /configs/PascalTitanX
parentbd2700c7a1b5be3e71ee2f0e9abab76719f2f462 (diff)
Need to make sure we don't kill the L1 too
Diffstat (limited to 'configs/PascalTitanX')
-rw-r--r--configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config2
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
index 2df24e1..f78bd02 100644
--- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
+++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
@@ -56,6 +56,8 @@
# Pascal GP102 has 64KB L1 cache
# The defulat is to disable the L1 cache, unless cache modifieres is used
-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16
-gpgpu_shmem_size 98304
-gpgpu_shmem_size_PrefL1 98304
-gpgpu_shmem_size_PrefShared 98304