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| author | Timothy G Rogers <[email protected]> | 2018-03-27 10:20:26 -0400 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2018-03-27 10:20:26 -0400 |
| commit | d936eadf3c10dc70cc89f59e36b9984a137c53cf (patch) | |
| tree | 40cecc895d6ba261428c530b4d99cec81d775206 /configs/PascalTitanX | |
| parent | 89c198ba1f271bfc12a6c7d9c471e62a8daa5634 (diff) | |
| parent | 28ac03ba1056718d9ec904f3b76319d8e9e2dfd0 (diff) | |
Merge branch 'dev-purdue-integration' into dev-purdue-integration
Diffstat (limited to 'configs/PascalTitanX')
| -rw-r--r-- | configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 28689ce..f78bd02 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -56,7 +56,11 @@ # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache |