diff options
| author | Rohan Mahapatra <[email protected]> | 2019-01-14 12:48:57 -0600 |
|---|---|---|
| committer | Rohan Mahapatra <[email protected]> | 2019-01-14 12:48:57 -0600 |
| commit | 5147dae0dfd32d4cbf71379d3504ce7b718712ec (patch) | |
| tree | e918dc1e96d0ae4cb59cc7298c181492f3abc035 /configs/deprecated-cfgs | |
| parent | d26501be3e3e8a6fe52409dd7cbaa7fa33e34d5e (diff) | |
Updated GTX1080 config file to conform to recent changes
with TensorCore pipeline stages and cache configuration.
Diffstat (limited to 'configs/deprecated-cfgs')
| -rw-r--r-- | configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config index fb044c6..3261d5a 100644 --- a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config +++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config @@ -31,12 +31,14 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP, ID_OC_DP, ID_OC_INT, ID_OC_SFU, ID_OC_MEM, OC_EX_SP, OC_EX_DP, OC_EX_INT, OC_EX_SFU, OC_EX_MEM, EX_WB ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_pipeline_widths 4,0,0,1,1,4,0,0,1,1,6 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 1 +-gpgpu_tensor_core_avail 0 +-gpgpu_num_tensor_core_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" @@ -54,20 +56,20 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:128:8,8 -gpgpu_shmem_size 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 -gpgpu_cache:dl2_texture_only 0 # 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units |