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authorMahmoud Khairy A. Abdallah <[email protected]>2020-04-02 21:23:07 -0400
committerMahmoud Khairy A. Abdallah <[email protected]>2020-04-02 21:23:07 -0400
commitf9e65c53a29b89c167e713afa6d5eb92709047af (patch)
treef3b2d5446a3069037c5ed1154123b5702e3c7bff /configs/tested-cfgs/SM3_KEPLER_TITAN
parentbd647361e2b8eb2d72f0055df851fcdee53e94cc (diff)
updating config files
Diffstat (limited to 'configs/tested-cfgs/SM3_KEPLER_TITAN')
-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config79
1 files changed, 38 insertions, 41 deletions
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
index 323d2d9..1951a3f 100644
--- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
@@ -18,12 +18,13 @@
-gpgpu_compute_capability_major 3
-gpgpu_compute_capability_minor 5
-# SASS execution (only supported with CUDA >= 4.0)
+# PTX execution-driven
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
+# SASS trace-driven mode execution
+#-trace_driven_mode 1
# high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster
-gpgpu_n_clusters 14
-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 12
@@ -46,15 +47,13 @@
# Pipeline widths and number of FUs
# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Kepler has 6 SP SIMD units and 2 SFU units per SM.
-# There is no int unit in kepler
-## we need to scale the number of pipeline registers to be equal to the number of SP units
+## Kepler has 6 SP SIMD units, 4 DPs and 2 SFU units per SM.
+# There is no INT unit in kepler
-gpgpu_pipeline_widths 6,4,0,2,1,6,4,0,2,1,12
-gpgpu_num_sp_units 6
-gpgpu_num_sfu_units 2
-gpgpu_num_dp_units 4
-
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
# All Div operations are executed on SFU unit
@@ -68,6 +67,38 @@
-ptx_opcode_initiation_sfu 2
-ptx_opcode_latency_sfu 200
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use kepler Coalsce arhitetecture
+-gpgpu_coalesce_arch 35
+
+## In Kepler, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 0
+
+# Kepler TITAN has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
@@ -97,37 +128,12 @@
# 4 KB Inst.
-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 8
# 48 KB Tex
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
# 12 KB Const
-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-# enable operand collector
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use kepler Coalsce arhitetecture
--gpgpu_coalesce_arch 35
-
-## In Kepler, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 0
-
# interconnection
-network_mode 1
-inter_config_file config_kepler_islip.icnt
@@ -161,15 +167,6 @@
#-Seperate_Write_Queue_Enable 1
#-Write_Queue_Size 64:56:32
-# Kepler TITAN has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
# stat collection
-gpgpu_memlatency_stat 14
-gpgpu_runtime_stat 500