updating config files

1 files changed, 39 insertions, 49 deletions

diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index f8689c2..d54b7d4 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -13,6 +13,7 @@
 -gpgpu_heap_size_limit 8388608
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
+-gpgpu_kernel_launch_latency 5000
 
 # Compute Capability
 -gpgpu_compute_capability_major 6
@@ -23,7 +24,6 @@
 -gpgpu_ptx_save_converted_ptxplus 0
 
 # high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
 -gpgpu_n_clusters 28
 -gpgpu_n_cores_per_cluster 1
 -gpgpu_n_mem 12
@@ -46,35 +46,58 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
-# There is no int unit in Pascal
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,0,4,1,4,1,0,4,1,9
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM.
+# There is no INT unit in Pascal
+-gpgpu_pipeline_widths 4,0,0,4,4,4,0,0,4,4,8
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 1
-
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_latency_int 4,13,4,4,145
 -ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_latency_fp 4,13,4,4,39
 -ptx_opcode_initiation_fp 1,2,1,1,4
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,8,8,8,130
 -ptx_opcode_initiation_sfu 4
 -ptx_opcode_latency_sfu 8
 
+# in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs
+-sub_core_model 1
+# enable operand collector 
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# 16 register banks, 4 banks per subcore
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
 
-# latencies and cache configs are adopted from:
-# https://arxiv.org/pdf/1804.06826.pdf
+## L1/shared memory configuration
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # The defulat is to disable the L1 cache, unless cache modifieres are used
+-l1_banks 2
 -gpgpu_cache:dl1  S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_cache:dl1PrefL1  S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_cache:dl1PrefShared  S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
@@ -92,45 +115,21 @@
 -gpgpu_flush_l1_cache 1
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2 S:1:128:1024,L:B:m:L:L,A:256:64,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 1
--memory_partition_indexing 0
+-memory_partition_indexing 4
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 8
 # 48 KB Tex 
 # Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use Pascal Coalsce arhitetecture
--gpgpu_coalesce_arch 61
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
+-perfect_inst_const_cache 1
 
 # interconnection
 -network_mode 1 
@@ -165,15 +164,6 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
 # stat collection
 -gpgpu_memlatency_stat 14 
 -gpgpu_runtime_stat 500