diff options
| author | Mahmoud <[email protected]> | 2018-11-07 20:30:02 -0500 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-11-07 20:30:02 -0500 |
| commit | 111cca2a061fe4f247be930cb44fdcdaec2b59f5 (patch) | |
| tree | 34f85262fabff8ccb8590a9c9eb57c1e88b5d4e8 /configs/tested-cfgs/SM6_TITANX | |
| parent | 7d42f5849aa1abb4f081803843ea78009d5b20ce (diff) | |
Adding INT unit, fixing tensor core latency, updating config files
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index ed35531..cb23ab3 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -35,10 +35,11 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs +# There is no int unit in Pascal ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5 -gpgpu_num_sp_units 2 -gpgpu_num_sfu_units 2 -gpgpu_num_dp_units 1 |