summaryrefslogtreecommitdiff
path: root/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt
diff options
context:
space:
mode:
authorMahmoud Khairy A. Abdallah <[email protected]>2020-04-02 21:23:07 -0400
committerMahmoud Khairy A. Abdallah <[email protected]>2020-04-02 21:23:07 -0400
commitf9e65c53a29b89c167e713afa6d5eb92709047af (patch)
treef3b2d5446a3069037c5ed1154123b5702e3c7bff /configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt
parentbd647361e2b8eb2d72f0055df851fcdee53e94cc (diff)
updating config files
Diffstat (limited to 'configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt')
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt73
1 files changed, 73 insertions, 0 deletions
diff --git a/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt
new file mode 100644
index 0000000..eed1c34
--- /dev/null
+++ b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt
@@ -0,0 +1,73 @@
+//52*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40;
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters = 1;
+
+credit_delay = 0;
+routing_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup = 1;
+output_speedup = 1;
+internal_speedup = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+