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| author | JRPan <[email protected]> | 2023-06-20 00:57:31 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-06-20 00:57:31 +0800 |
| commit | 3d936e50a83787af07bf2b2527c4d16ad454ecf9 (patch) | |
| tree | 1c032284606054bfd7fe94a6ded92e223e19fc37 /configs/tested-cfgs/SM7_TITANV/gpgpusim.config | |
| parent | ccf6662429efcfcf28d1050455163e41553a31f6 (diff) | |
| parent | 301be9e59c6c934f4e194cf6c95dd0c60b3894cc (diff) | |
Merge branch 'dev' into compare_warn
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index af561de..c37aaf0 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -107,7 +107,7 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory # In Volta, we assign the remaining shared memory to L1 cache |