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| author | mkhairy <[email protected]> | 2021-05-19 22:26:33 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-05-19 22:26:33 -0400 |
| commit | 2aef4e3d5a662d04da03ec782b116d16a5bcc012 (patch) | |
| tree | 58910c0e1d58f9528f50affb1354ae072ffc4adf /configs/tested-cfgs/SM7_TITANV | |
| parent | 604baaf59255776b4714c0270ce36ad823d34df4 (diff) | |
| parent | 0d33266ff6ca9b880dff40f6338c8a5cae696438 (diff) | |
Merge pull request #16 from mkhairy/dev
Updating config files and code refactoring of Junuri's code
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 32245d7..c44563f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -114,20 +114,21 @@ # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution -gpgpu_adaptive_cache_config 1 -# Volta unified cache has four banks +-gpgpu_shmem_option 0,8,16,32,64,96 +-gpgpu_unified_l1d_size 128 +# L1 cache configuration -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 +-gpgpu_l1_cache_write_ratio 25 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_l1_latency 20 +-gpgpu_flush_l1_cache 1 +-gpgpu_n_cluster_ejection_buffer_size 32 +# shared memory configuration -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 20 -gpgpu_smem_latency 20 --gpgpu_flush_l1_cache 1 --gpgpu_l1_cache_write_ratio 25 --gpgpu_shmem_option 0,12,24,48,96 --gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 |