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| author | Tim Rogers <[email protected]> | 2019-05-02 16:11:34 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-05-02 16:11:34 -0400 |
| commit | 4697483b3fffcdfcf81a4199d87c1255a8b55729 (patch) | |
| tree | 3e422d596167ebde1a0fdf9994bee87d66843426 /configs/tested-cfgs/SM7_TITANV | |
| parent | bbef52a122761bc8f02092e0acf867dbd87cbe70 (diff) | |
| parent | f507979bcf0f14d1e5843c9b08613d6b0a4bb7a2 (diff) | |
Merge branch 'dev' into dev
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 13d8c8f..ae35fef 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -86,7 +86,7 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adpative_volta_cache_config 1 +-adaptive_volta_cache_config 1 # Volta unified cache has four ports -mem_unit_ports 4 -gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 |