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authorTor Aamodt <[email protected]>2010-10-19 23:10:51 -0800
committerTor Aamodt <[email protected]>2010-10-19 23:10:51 -0800
commitee5ea34857e4ecc6c63d4971e549076c6a9888ba (patch)
tree6931d8981a4179b479cfdc43cd3ec3972e754d9d /configs
parent6c65cb0119ca7c84993cab6b8828687e1b331bd0 (diff)
adding texture cache model with fragment fifo for latency hiding
passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
Diffstat (limited to 'configs')
-rw-r--r--configs/QuadroFX5800/gpgpusim.config13
1 files changed, 4 insertions, 9 deletions
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index f8d27f5..6f1c936 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -17,18 +17,13 @@
-gpgpu_simd_model 1
# memory stage behaviour
--gpgpu_no_dl1 1
--gpgpu_n_cache_bank 1
--gpgpu_cache:dl1 128:64:4:L:T:m
--gpgpu_tex_cache:l1 8:32:20:L:R:m
--gpgpu_const_cache:l1 64:64:2:L:R:f
--gpgpu_cache:dl2 64:32:8:L:R:m
+-gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4
+-gpgpu_tex_cache:l1 8:32:20:L:R:m,F:128:4,16:2
+-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4
+-gpgpu_cache:dl2 64:32:8:L:R:m,A:16:4,4
-gpgpu_shmem_pipe_speedup 2
-gpgpu_shmem_port_per_bank 2
--gpgpu_cache_port_per_bank 2
--gpgpu_const_port_per_bank 2
--gpgpu_interwarp_mshr_merge 6
# interconnection
-network_mode 1