diff options
| author | aamir <[email protected]> | 2018-09-09 15:10:06 -0700 |
|---|---|---|
| committer | aamir <[email protected]> | 2018-09-09 15:10:06 -0700 |
| commit | 7a77d951e6a900d61436df12826bb677aeaee6e6 (patch) | |
| tree | c60e6ad27d4f4da273fdd8ceeae633b17e0e0273 /cutlass-example | |
| parent | 242f3fd369f6ea3f0e808dd5d6446a294e63d9aa (diff) | |
minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED
Diffstat (limited to 'cutlass-example')
| -rw-r--r-- | cutlass-example/gpgpusim.config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cutlass-example/gpgpusim.config b/cutlass-example/gpgpusim.config index 2510d21..3daa539 100644 --- a/cutlass-example/gpgpusim.config +++ b/cutlass-example/gpgpusim.config @@ -33,7 +33,7 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,6 +-gpgpu_pipeline_widths 4,1,1,1,1,4,1,1,1,1,6 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 1 # Instruction latencies and initiation intervals |