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authorTim Rogers <[email protected]>2011-10-27 09:01:15 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:18:23 -0700
commitf76b1aaeea5077e83f95ef39564e73bcbec25b37 (patch)
treec41d6fab7551854960a7342239791dea174d6be0 /libopencl
parent52047f8c7ac9fa2ce47b5b59d1539a3b494a370f (diff)
Fixing the varying instruction count when the cache configuration changes.
The problem was 2-fold: 1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count. 2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737]
Diffstat (limited to 'libopencl')
0 files changed, 0 insertions, 0 deletions