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authoraamir <[email protected]>2018-09-09 15:10:06 -0700
committeraamir <[email protected]>2018-09-09 15:10:06 -0700
commit7a77d951e6a900d61436df12826bb677aeaee6e6 (patch)
treec60e6ad27d4f4da273fdd8ceeae633b17e0e0273 /src/abstract_hardware_model.cc
parent242f3fd369f6ea3f0e808dd5d6446a294e63d9aa (diff)
minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED
Diffstat (limited to 'src/abstract_hardware_model.cc')
-rw-r--r--src/abstract_hardware_model.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index d668de7..b24a77e 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -184,7 +184,7 @@ void warp_inst_t::generate_mem_accesses()
{
if( empty() || op == MEMORY_BARRIER_OP || m_mem_accesses_created )
return;
- if ( !((op == LOAD_OP) || (op == STORE_OP)) )
+ if (!((op == LOAD_OP) || (op==TENSOR_CORE_LOAD_OP) || (op==VP_LOAD_OP) || (op == STORE_OP)||(op==TENSOR_CORE_STORE_OP)||(op==VP_STORE_OP)))
return;
if( m_warp_active_mask.count() == 0 )
return; // predicated off