summaryrefslogtreecommitdiff
path: root/src/abstract_hardware_model.h
diff options
context:
space:
mode:
authorMahmoud <[email protected]>2019-08-30 18:43:21 -0400
committerMahmoud <[email protected]>2019-08-30 18:43:21 -0400
commit93597743b24b7d7726096d337e6c9c4516cb2273 (patch)
treea9bca57c102d11edb3a8d878324db5a810caef60 /src/abstract_hardware_model.h
parent2e2b0911f8cc9d172e4602765ce4c20ffb583cf0 (diff)
update the adaptive cache behaviour and make L1 fully assoc in Volta
Diffstat (limited to 'src/abstract_hardware_model.h')
-rw-r--r--src/abstract_hardware_model.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 27a1ba6..231b6a2 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -65,6 +65,11 @@ enum FuncCache
FuncCachePreferL1 = 2
};
+enum AdaptiveCache
+{
+ FIXED = 0,
+ VOLTA = 1
+};
#ifdef __cplusplus
@@ -345,7 +350,7 @@ public:
unsigned long long end_cycle;
unsigned m_launch_latency;
- mutable bool volta_cache_config_set;
+ mutable bool cache_config_set;
};
struct core_config {
@@ -388,7 +393,7 @@ struct core_config {
unsigned gpgpu_max_insn_issue_per_warp;
bool gmem_skip_L1D; // on = global memory access always skip the L1 cache
- bool adaptive_volta_cache_config;
+ unsigned adaptive_cache_config;
};
// bounded stack that implements simt reconvergence using pdom mechanism from MICRO'07 paper