diff options
| author | Wilson Fung <[email protected]> | 2012-11-02 04:00:26 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:49:21 -0700 |
| commit | 9af6f86d0f06c2ca1b117d358009b91a646b0e83 (patch) | |
| tree | 10509be824e0ba4d41e826138ae7225c9c3fd43c /src/cuda-sim/cuda-sim.cc | |
| parent | d0b377ded0c804580a78f2327b84e6e2ea1ee069 (diff) | |
Fixed the timing model for LDU instruction, before it was not recognized as a memory instruction in the timing model.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14538]
Diffstat (limited to 'src/cuda-sim/cuda-sim.cc')
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 06fb7d3..85afe73 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -495,6 +495,7 @@ void ptx_instruction::set_opcode_and_latency() if ( has_memory_write() ) op = STORE_OP; break; case LD_OP: op = LOAD_OP; break; + case LDU_OP: op = LOAD_OP; break; case ST_OP: op = STORE_OP; break; case BRA_OP: op = BRANCH_OP; break; case BREAKADDR_OP: op = BRANCH_OP; break; @@ -724,7 +725,7 @@ void ptx_instruction::pre_decode() case WB_OPTION: cache_op = CACHE_WRITE_BACK; break; case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; default: - if( m_opcode == LD_OP ) + if( m_opcode == LD_OP || m_opcode == LDU_OP ) cache_op = CACHE_ALL; else if( m_opcode == ST_OP ) cache_op = CACHE_WRITE_BACK; |