diff options
| author | Md Aamir Raihan <[email protected]> | 2018-10-26 11:39:26 -0700 |
|---|---|---|
| committer | Md Aamir Raihan <[email protected]> | 2018-10-26 11:39:26 -0700 |
| commit | aeb78a3dcd5613404162514e98d18ee9dbf31569 (patch) | |
| tree | 26b83d68e30d89670310484174444ff3188e7753 /src/cuda-sim/cuda-sim.cc | |
| parent | 7c441c450e40bf07bdf1acfe1eb2258952e1f7b7 (diff) | |
made the changes compatible with old config files
Diffstat (limited to 'src/cuda-sim/cuda-sim.cc')
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 7587db7..86a1d45 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -69,9 +69,9 @@ unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>" - "Default 1,1,19,25,145,1,4", - "1,1,19,25,145,1,4"); + "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>" + "Default 1,1,19,25,145", + "1,1,19,25,145"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>" "Default 1,1,1,1,30", @@ -81,9 +81,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>" - "Default 1,1,4,4,32,1,1", - "1,1,4,4,32,1"); + "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>" + "Default 1,1,4,4,32", + "1,1,4,4,32"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>" "Default 1,1,1,1,5", @@ -590,13 +590,9 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { unsigned int_latency[5]; - unsigned int_precision; - unsigned int_lane_width; unsigned fp_latency[5]; unsigned dp_latency[5]; unsigned int_init[5]; - unsigned int_init_precision; - unsigned int_init_lane_width; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -605,11 +601,10 @@ void ptx_instruction::set_opcode_and_latency() * [2] MUL * [3] MAD * [4] DIV - * [5] BSMAD */ sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4],&int_precision,&int_lane_width); + &int_latency[3],&int_latency[4]); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); @@ -618,7 +613,7 @@ void ptx_instruction::set_opcode_and_latency() &dp_latency[3],&dp_latency[4]); sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4],&int_init_precision,&int_init_lane_width); + &int_init[3],&int_init[4]); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); |