diff options
| author | Ahmed El-Shafiey <[email protected]> | 2013-05-20 14:08:21 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:50:47 -0700 |
| commit | a223bc92293cf4c8d0e45ca6f15acdc571755ee5 (patch) | |
| tree | 561f7edca64d4865eb8dbf02b2a1cecab2f0aa89 /src/cuda-sim | |
| parent | 6d4f367f91dfaf9ea235f9fef25afb04de008c86 (diff) | |
Fixing bug 59 + cleaning some code related to the power model
Review ID:32001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16205]
Diffstat (limited to 'src/cuda-sim')
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 5c66c7a..a7294c1 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -467,52 +467,52 @@ std::string ptx_get_insn_str( address_type pc ) } void ptx_instruction::set_fp_or_int_archop(){ - op2=UN_OP; + oprnd_type=UN_OP; if((m_opcode == MEMBAR_OP)||(m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){ // do nothing }else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){ if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){ - op2= FP_OP; - }else op2=INT_OP; + oprnd_type= FP_OP; + }else oprnd_type=INT_OP; }else{ if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ - op2= FP_OP; - }else op2=INT_OP; + oprnd_type= FP_OP; + }else oprnd_type=INT_OP; } } void ptx_instruction::set_mul_div_or_other_archop(){ - op3=OTHER_OP; + sp_op=OTHER_OP; if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){ if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ switch(get_opcode()){ case MUL_OP: case MAD_OP: - op3=FP_MUL_OP; + sp_op=FP_MUL_OP; break; case DIV_OP: - op3=FP_DIV_OP; + sp_op=FP_DIV_OP; break; case LG2_OP: - op3=FP_LG_OP; + sp_op=FP_LG_OP; break; case RSQRT_OP: case SQRT_OP: - op3=FP_SQRT_OP; + sp_op=FP_SQRT_OP; break; case RCP_OP: - op3=FP_DIV_OP; + sp_op=FP_DIV_OP; break; case SIN_OP: case COS_OP: - op3=FP_SIN_OP; + sp_op=FP_SIN_OP; break; case EX2_OP: - op3=FP_EXP_OP; + sp_op=FP_EXP_OP; break; default: if(op==ALU_OP) - op3=FP__OP; + sp_op=FP__OP; break; } @@ -520,21 +520,21 @@ void ptx_instruction::set_mul_div_or_other_archop(){ switch(get_opcode()){ case MUL24_OP: case MAD24_OP: - op3=INT_MUL24_OP; + sp_op=INT_MUL24_OP; break; case MUL_OP: case MAD_OP: if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE) - op3=INT_MUL32_OP; + sp_op=INT_MUL32_OP; else - op3=INT_MUL_OP; + sp_op=INT_MUL_OP; break; case DIV_OP: - op3=INT_DIV_OP; + sp_op=INT_DIV_OP; break; default: if(op==ALU_OP) - op3=INT__OP; + sp_op=INT__OP; break; } } @@ -585,7 +585,7 @@ void ptx_instruction::set_opcode_and_latency() } } op = ALU_OP; - op5= NOT_TEX; + mem_op= NOT_TEX; initiation_interval = latency = 1; switch( m_opcode ) { case MOV_OP: @@ -598,7 +598,7 @@ void ptx_instruction::set_opcode_and_latency() case ST_OP: op = STORE_OP; break; case BRA_OP: op = BRANCH_OP; break; case BREAKADDR_OP: op = BRANCH_OP; break; - case TEX_OP: op = LOAD_OP; op5=TEX; break; + case TEX_OP: op = LOAD_OP; mem_op=TEX; break; case ATOM_OP: op = LOAD_OP; break; case BAR_OP: op = BARRIER_OP; break; case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; |