diff options
| author | Wilson Fung <[email protected]> | 2011-08-02 14:25:44 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:18:22 -0700 |
| commit | 0b65fd56c3e9c7e5d3fe22ff17b594bb84e9af69 (patch) | |
| tree | 86806c3a9536e426997e9bc33474d5fc31a865f9 /src/gpgpu-sim/dram.cc | |
| parent | 8eb9ab667645ca32174093927f5e3b25368c752e (diff) | |
Fixed the DRAM timing model to add the write-read turn and write-precharge delay. Still need to update/validate the Quadro config for this.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
Diffstat (limited to 'src/gpgpu-sim/dram.cc')
| -rw-r--r-- | src/gpgpu-sim/dram.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index fb95673..b09033f 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -294,6 +294,8 @@ void dram_t::cycle() bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; /*16 bytes*/ CCDc = m_config->tCCD; + WTRc = m_config->tWTR; + bk[j]->WTPc = m_config->tWTP; issued = true; n_wr++; bwutil+=2; @@ -339,7 +341,7 @@ void dram_t::cycle() if ( (!issued) && (bk[j]->curr_row != bk[j]->mrq->row) && (bk[j]->state == BANK_ACTIVE) && - (!bk[j]->RASc) ) { + (!bk[j]->RASc && !bk[j]->WTPc) ) { // make the bank idle again bk[j]->state = BANK_IDLE; bk[j]->RPc = m_config->tRP; @@ -383,6 +385,7 @@ void dram_t::cycle() DEC2ZERO(bk[j]->RCc); DEC2ZERO(bk[j]->RPc); DEC2ZERO(bk[j]->RCDWRc); + DEC2ZERO(bk[j]->WTPc); } #ifdef DRAM_VISUALIZE |