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authorMahmoud <[email protected]>2019-08-30 18:43:21 -0400
committerMahmoud <[email protected]>2019-08-30 18:43:21 -0400
commit93597743b24b7d7726096d337e6c9c4516cb2273 (patch)
treea9bca57c102d11edb3a8d878324db5a810caef60 /src/gpgpu-sim/gpu-cache.cc
parent2e2b0911f8cc9d172e4602765ce4c20ffb583cf0 (diff)
update the adaptive cache behaviour and make L1 fully assoc in Volta
Diffstat (limited to 'src/gpgpu-sim/gpu-cache.cc')
-rw-r--r--src/gpgpu-sim/gpu-cache.cc7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index db9701d..8d00ea9 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -65,8 +65,13 @@ const char * cache_fail_status_str(enum cache_reservation_fail_reason status)
unsigned l1d_cache_config::set_bank(new_addr_type addr) const{
- if(m_cache_type == SECTOR)
+ //For sector cache, we select one sector per bank (sector interleaving)
+ //This is what was found in Volta (one sector per bank, sector interleaving)
+ //otherwise, line interleaving
+ if(m_cache_type == SECTOR) {
+ //assert(l1_banks == SECTOR_CHUNCK_SIZE);
return (addr >> m_sector_sz_log2) & (l1_banks-1);
+ }
else
return (addr >> m_line_sz_log2) & (l1_banks-1);
}