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authorMahmoud <[email protected]>2019-08-26 12:17:52 -0400
committerMahmoud <[email protected]>2019-08-26 12:17:52 -0400
commitc2a1e3a668f9a88239184e13460f7e1725b15c90 (patch)
tree0546cc50d6e222072add55e36999a338b925d807 /src/gpgpu-sim/gpu-cache.cc
parent56c52cf6c4b369e9fd05759e9b16ea37ff6e332c (diff)
Banked L1, adding iSLIP and RR arbiteratio and adding some comments
Diffstat (limited to 'src/gpgpu-sim/gpu-cache.cc')
-rw-r--r--src/gpgpu-sim/gpu-cache.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 370f6e6..db9701d 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -63,6 +63,14 @@ const char * cache_fail_status_str(enum cache_reservation_fail_reason status)
return static_cache_reservation_fail_reason_str[status];
}
+unsigned l1d_cache_config::set_bank(new_addr_type addr) const{
+
+ if(m_cache_type == SECTOR)
+ return (addr >> m_sector_sz_log2) & (l1_banks-1);
+ else
+ return (addr >> m_line_sz_log2) & (l1_banks-1);
+}
+
unsigned l1d_cache_config::set_index(new_addr_type addr) const{
unsigned set_index = m_nset; // Default to linear set index function
unsigned lower_xor = 0;