diff options
| author | Tayler Hetherington <[email protected]> | 2012-10-15 14:49:25 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:49:21 -0700 |
| commit | 1ade3b340c72f65fe01735df0748e13d4c026998 (patch) | |
| tree | 126380106a0d7793b321d36f9964b2a21cb9cd30 /src/gpgpu-sim/gpu-sim.cc | |
| parent | 6dfa8ae94d4497ad6b026eb2ce9ba8926566353e (diff) | |
- Fixing cache configuration groupings -> Now <cache configs>, <cache policies>, <MSHR>, <Miss queue/FIFO sizing>
- Fixing default configurations to match the new format and additonal parameters
- Fixing Fermi's 48kB cache configuration
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 6d9fa87..9c8d327 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -99,8 +99,8 @@ void memory_config::reg_options(class OptionParser * opp) "0"); option_parser_register(opp, "-gpgpu_cache:dl2", OPT_CSTR, &m_L2_config.m_config_string, "unified banked L2 data cache config " - " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>}", - "64:128:8:L:R:m,A:16:4,4"); + " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}", + "64:128:8,L:B:m:N,A:16:4,4"); option_parser_register(opp, "-gpgpu_cache:dl2_texture_only", OPT_BOOL, &m_L2_texure_only, "L2 cache used for texture only", "1"); @@ -147,19 +147,19 @@ void shader_core_config::reg_options(class OptionParser * opp) "1024:32"); option_parser_register(opp, "-gpgpu_tex_cache:l1", OPT_CSTR, &m_L1T_config.m_config_string, "per-shader L1 texture cache (READ-ONLY) config " - " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}", - "8:128:5:L:R:m,F:128:4,128:2"); + " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}", + "8:128:5,L:R:m:N,F:128:4,128:2"); option_parser_register(opp, "-gpgpu_const_cache:l1", OPT_CSTR, &m_L1C_config.m_config_string, "per-shader L1 constant memory cache (READ-ONLY) config " - " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>}", - "64:64:2:L:R:f,A:2:32,4" ); + " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} ", + "64:64:2,L:R:f:N,A:2:32,4" ); option_parser_register(opp, "-gpgpu_cache:il1", OPT_CSTR, &m_L1I_config.m_config_string, "shader L1 instruction cache config " - " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>}", - "4:256:4:L:R:f,A:2:32,4" ); + " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} ", + "4:256:4,L:R:f:N,A:2:32,4" ); option_parser_register(opp, "-gpgpu_cache:dl1", OPT_CSTR, &m_L1D_config.m_config_string, "per-shader L1 data cache config " - " {<nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>|none}", + " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); option_parser_register(opp, "-gpgpu_perfect_mem", OPT_BOOL, &gpgpu_perfect_mem, "enable perfect memory mode (no cache miss)", |