diff options
| author | Wilson Fung <[email protected]> | 2012-06-18 21:59:31 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:47:32 -0700 |
| commit | dad9e2a5cfb0f1f49279a6d2746454dd32f6eb85 (patch) | |
| tree | 46a717e2bbba89b90ae5c737aae7caeb7e4b4bcd /src/gpgpu-sim/gpu-sim.cc | |
| parent | 46716354407900581e86fa3537ce156f45d340ae (diff) | |
Fixed GDDR5 parameters in Fermi config:
- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
- Decreased the DRAM clock to 924MHz from 1848MHz.
- Corrected CAS Latency and Write Latency in the timing constraints.
- Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index cffec45..35070d8 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -120,8 +120,11 @@ void memory_config::reg_options(class OptionParser * opp) "default = 4 bytes (8 bytes per cycle at DDR)", "4"); option_parser_register(opp, "-gpgpu_dram_burst_length", OPT_UINT32, &BL, - "Burst length of each DRAM request (default = 4 DDR cycle)", + "Burst length of each DRAM request (default = 4 data bus cycle)", "4"); + option_parser_register(opp, "-dram_data_command_freq_ratio", OPT_UINT32, &data_command_freq_ratio, + "Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)", + "2"); option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); |