adding texture cache model with fragment fifo for latency hiding

passing CUDA 3.1 regression

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]

1 files changed, 1 insertions, 1 deletions

diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index 6900394..7d1a8b2 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -103,7 +103,7 @@ private:
    unsigned m_id;
    const struct memory_config *m_config;
    class dram_t *m_dram;
-   class cache_t *m_L2cache;
+   class read_only_cache *m_L2cache;
    class L2interface *m_L2interface;
 
    // model delay of ROP units with a fixed latency