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authorTor Aamodt <[email protected]>2010-11-28 20:48:33 -0800
committerTor Aamodt <[email protected]>2010-11-28 20:48:33 -0800
commit6e06c2e1de8c51a88845b7f35cea219dca7456f2 (patch)
tree28b3daed248f3f4dca9ca49f9d939f6edae10238 /src/gpgpu-sim/mem_fetch.cc
parent23d096dd1f1d4f0387087ffff0605fbf349556d2 (diff)
enabling L2 data cache... it is write through, write evict like L1.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
Diffstat (limited to 'src/gpgpu-sim/mem_fetch.cc')
-rw-r--r--src/gpgpu-sim/mem_fetch.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc
index f4c3bcc..699ba0a 100644
--- a/src/gpgpu-sim/mem_fetch.cc
+++ b/src/gpgpu-sim/mem_fetch.cc
@@ -92,7 +92,7 @@ mem_fetch::mem_fetch( const mem_access_t &access,
m_wid = wid;
config->m_address_mapping.addrdec_tlx(access.get_addr(),&m_raw_addr);
m_partition_addr = config->m_address_mapping.partition_address(access.get_addr());
- m_type = m_access.is_write()?WR_REQ:RD_REQ;
+ m_type = m_access.is_write()?WRITE_REQUEST:READ_REQUEST;
m_timestamp = gpu_sim_cycle + gpu_tot_sim_cycle;
m_timestamp2 = 0;
m_status = MEM_FETCH_INITIALIZED;