diff options
| author | Tor Aamodt <[email protected]> | 2010-10-21 07:16:49 -0800 |
|---|---|---|
| committer | Tor Aamodt <[email protected]> | 2010-10-21 07:16:49 -0800 |
| commit | dc93f319051a9a9936a02cd9c1f7843a382a2da0 (patch) | |
| tree | 6c042ccab67be43b8fe442ab435ffbfd0f34e56e /src/gpgpu-sim/mem_latency_stat.cc | |
| parent | ee5ea34857e4ecc6c63d4971e549076c6a9888ba (diff) | |
1. rewriting memory access generation code (from scratch), why not...
passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)...
after debugging 1 to get it working with ptxplus, problem is very clear:
shared and constant cache accesses not occuring for operations that combine these with ALU operations.
TODO:
have a "read-operands" stage, which somehow combines operand collector
register reading with shared and const memory accesses...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
Diffstat (limited to 'src/gpgpu-sim/mem_latency_stat.cc')
| -rw-r--r-- | src/gpgpu-sim/mem_latency_stat.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index f78717e..5b4d3ac 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -229,7 +229,7 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf) } if (mf->get_pc() != (unsigned)-1) ptx_file_line_stats_add_dram_traffic(mf->get_pc(),1); - mem_access_type_stats[mf->get_mem_acc()][dram_id][bank]++; + mem_access_type_stats[mf->get_access_type()][dram_id][bank]++; } } |