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authorTayler Hetherington <[email protected]>2012-11-30 21:29:42 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:49:22 -0700
commit36ce0f2243fd0723a746b3c2f5f0651577312400 (patch)
treee79475e75f800ad34b4851ea710c4ee409f5bd72 /src/gpgpu-sim/mem_latency_stat.h
parent08ec3343d0bca75e63e130266f75f8242f22050b (diff)
Merging Power model into Fermi
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
Diffstat (limited to 'src/gpgpu-sim/mem_latency_stat.h')
-rw-r--r--src/gpgpu-sim/mem_latency_stat.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 95017d8..83114fa 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -82,9 +82,9 @@ public:
// stats
+ unsigned L2_write_access;
unsigned L2_write_miss;
- unsigned L2_write_hit;
- unsigned L2_read_hit;
+ unsigned L2_read_access;
unsigned L2_read_miss;
unsigned int *L2_cbtoL2length;
unsigned int *L2_cbtoL2writelength;
@@ -98,6 +98,11 @@ public:
unsigned int **row_access; //row_access[dram chip id][bank id]
unsigned int **max_conc_access2samerow; //max_conc_access2samerow[dram chip id][bank id]
unsigned int **max_servicetime2samerow; //max_servicetime2samerow[dram chip id][bank id]
+
+ // Power stats
+ unsigned total_n_access;
+ unsigned total_n_reads;
+ unsigned total_n_writes;
};
#endif /*MEM_LATENCY_STAT_H*/