diff options
| author | Mahmoud <[email protected]> | 2019-11-15 20:08:28 -0500 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-11-15 20:08:28 -0500 |
| commit | 4702017e7597fc31cb4f2337aa5d9e8ba8287418 (patch) | |
| tree | 133bcd4c81ade9f644b0e34e3523278271ed39e9 /src/gpgpu-sim/shader.cc | |
| parent | d3316efe70f6007d15f81f828bb5fc82bc5c86d4 (diff) | |
invalidate l1 cache at membar - fixing
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 19f8e72..0ea819d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3470,8 +3470,9 @@ bool shader_core_ctx::warp_waiting_at_mem_barrier( unsigned warp_id ) return false; if( !m_scoreboard->pendingWrites(warp_id) ) { m_warp[warp_id].clear_membar(); - if (m_gpu->get_config().gpgpu_flush_l1_cache) { - //invalidate L1 cache + if (m_gpu->get_config().flush_l1()) { + //Mahmoud fixed this on Nov 2019 + //Invalidate L1 cache //Based on Nvidia Doc, at MEM barrier, we have to //(1) wait for all pending writes till they are acked //(2) invalidate L1 cache to ensure coherence and avoid reading stall data |