add simple simd lane set partitioning

1 files changed, 33 insertions, 1 deletions

diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index bcf38d3..9f92215 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1052,8 +1052,35 @@ void shader_core_ctx::fetch() {
   m_L1I->cycle();
 }
 
+void exec_shader_core_ctx::execute_warp_inst_per_set(warp_inst_t &inst) {
+  // Execute each SIMD set's threads independently
+  const std::vector<simd_set_info> &sets = inst.get_simd_sets();
+  unsigned warp_id = inst.warp_id();
+  unsigned set_width = m_config->simd_set_width;
+
+  for (unsigned s = 0; s < sets.size(); s++) {
+    const simd_set_info &set = sets[s];
+    if (!set.valid) continue;
+
+    // Execute each active thread in this set
+    for (unsigned lane = 0; lane < set_width; lane++) {
+      if (set.set_active_mask.test(lane)) {
+        unsigned t = set.thread_ids[lane];  // original thread position (0-31)
+        unsigned hw_tid = m_warp_size * warp_id + t;
+        assert(inst.active(t));  // thread must be active in original mask
+        m_thread[hw_tid]->ptx_exec_inst(inst, t);
+        checkExecutionStatusAndUpdate(inst, t, hw_tid);
+      }
+    }
+  }
+}
+
 void exec_shader_core_ctx::func_exec_inst(warp_inst_t &inst) {
-  execute_warp_inst_t(inst);
+  if (m_config->gpgpu_simd_partitioning && inst.has_simd_sets()) {
+    execute_warp_inst_per_set(inst);
+  } else {
+    execute_warp_inst_t(inst);
+  }
   if (inst.is_load() || inst.is_store()) {
     inst.generate_mem_accesses();
     // inst.print_m_accessq();
@@ -1076,6 +1103,11 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
       m_warp[warp_id]->get_dynamic_warp_id(), sch_id,
       m_warp[warp_id]->get_streamID());  // dynamic instruction information
   m_stats->shader_cycle_distro[2 + (*pipe_reg)->active_count()]++;
+  // Compute SIMD set assignments before functional execution
+  if (m_config->gpgpu_simd_partitioning) {
+    (*pipe_reg)->compute_simd_sets(m_config->gpgpu_num_simd_sets,
+                                   m_config->simd_set_width);
+  }
   func_exec_inst(**pipe_reg);
 
   // Add LDGSTS instructions into a buffer