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authorTayler Hetherington <[email protected]>2012-09-19 14:51:45 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:49:20 -0700
commitb09eeed6aa36239f661d6452e996e3e5f8ef5984 (patch)
tree1d71f118193e7eb8b8de79d3f08a934067e5a143 /src/gpgpu-sim/shader.cc
parentb19fd89f07b3221ea73f6c2442880c2e5c1e68a5 (diff)
Revision #2 of modifying the cache hierarchy.
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
-rw-r--r--src/gpgpu-sim/shader.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 7b65add..0dd8fd0 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1122,7 +1122,7 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
m_L1C = new read_only_cache(L1C_name,m_config->m_L1C_config,m_sid,get_shader_constant_cache_id(),icnt,IN_L1C_MISS_QUEUE);
m_L1D = NULL;
if( !m_config->m_L1D_config.disabled() )
- m_L1D = new data_cache(L1D_name,m_config->m_L1D_config,m_sid,get_shader_normal_cache_id(),m_icnt,m_mf_allocator,IN_L1D_MISS_QUEUE);
+ m_L1D = new l1_cache(L1D_name,m_config->m_L1D_config,m_sid,get_shader_normal_cache_id(),m_icnt,m_mf_allocator,IN_L1D_MISS_QUEUE);
m_mem_rc = NO_RC_FAIL;
m_num_writeback_clients=5; // = shared memory, global/local (uncached), L1D, L1T, L1C
m_writeback_arb = 0;