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authorAhmad Alawneh <[email protected]>2023-06-06 22:58:29 -0400
committerAhmad Alawneh <[email protected]>2023-06-12 20:31:30 -0400
commite700b1816492bb811e5aa12d1b1b0ec778e04235 (patch)
treed5c0ab109525ec80a4b407b02be8d1d2a1540a72 /src/gpgpu-sim/shader.cc
parentce5c443efa2ec72b7d7b88210eea71db89b29c89 (diff)
fix types, change int to unsigned int
Diffstat (limited to 'src/gpgpu-sim/shader.cc')
-rw-r--r--src/gpgpu-sim/shader.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 4ae0f62..fdc7f77 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -107,7 +107,7 @@ void shader_core_ctx::create_front_pipeline() {
m_pipeline_reg.push_back(
register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j]));
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -115,7 +115,7 @@ void shader_core_ctx::create_front_pipeline() {
m_specilized_dispatch_reg.push_back(
&m_pipeline_reg[m_pipeline_reg.size() - 1]);
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -140,7 +140,7 @@ void shader_core_ctx::create_front_pipeline() {
if (m_config->gpgpu_num_int_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_INT].get_size());
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
if (m_config->m_specialized_unit[j].num_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_config->m_specialized_unit[j].id_oc_spec_reg_width);