diff options
| author | Tor Aamodt <[email protected]> | 2010-10-18 02:43:17 -0800 |
|---|---|---|
| committer | Tor Aamodt <[email protected]> | 2010-10-18 02:43:17 -0800 |
| commit | 87e4da5fc6086c3d0a661af1929255a8cbd728d7 (patch) | |
| tree | a4f40e66f5ca0d6efdf9d51672a1180c8a381170 /src/gpgpu-sim/stats.h | |
| parent | b577cbcdf229a2c02d1bf8584c6e82be7a14cb33 (diff) | |
Re-designed cache model:
- read only cache model with integrated mshrs (no L1D, yet); new
cache interface should be easily extendable to support texture
cache with latency fifo and separate tag/data arrays, though
this is not yet added (currently tags and data arrays are not
decoupled for texture)
- new partition model using the above
removes all old MSHRs, L1D etc...
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
Diffstat (limited to 'src/gpgpu-sim/stats.h')
| -rw-r--r-- | src/gpgpu-sim/stats.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/gpgpu-sim/stats.h b/src/gpgpu-sim/stats.h index 8115eae..0abdb22 100644 --- a/src/gpgpu-sim/stats.h +++ b/src/gpgpu-sim/stats.h @@ -102,7 +102,6 @@ struct shader_core_stats unsigned int gpgpu_n_cache_bkconflict; int gpgpu_n_intrawarp_mshr_merge; unsigned int gpgpu_n_cmem_portconflict; - int gpgpu_n_partial_writes; unsigned int gpu_stall_shd_mem_breakdown[N_MEM_STAGE_ACCESS_TYPE][N_MEM_STAGE_STALL_TYPE]; unsigned int gpu_reg_bank_conflict_stalls; unsigned int *shader_cycle_distro; |