diff options
| author | Wilson Fung <[email protected]> | 2012-01-13 04:40:12 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:19:02 -0700 |
| commit | 109ce04bac832fa51217750ec9b48aaa7641bc4e (patch) | |
| tree | 3dcda0a96aa19c774fb88c6a2ad9804e469b4a85 /src/gpgpu-sim | |
| parent | 576bdb124dbf52345246adbc290dabac4bd25b35 (diff) | |
Revived all of the source code view stats except exposed pipeline latency.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11329]
Diffstat (limited to 'src/gpgpu-sim')
| -rw-r--r-- | src/gpgpu-sim/mem_latency_stat.cc | 4 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 9 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index b23919e..68cd850 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -181,10 +181,10 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf) shader_mem_acc_log( mf->get_sid(), dram_id, bank, 'r'); totalbankreads[dram_id][bank]++; } - if (mf->get_pc() != (unsigned)-1) - ptx_file_line_stats_add_dram_traffic(mf->get_pc(),1); mem_access_type_stats[mf->get_access_type()][dram_id][bank]++; } + if (mf->get_pc() != (unsigned)-1) + ptx_file_line_stats_add_dram_traffic(mf->get_pc(), mf->get_data_size()); } void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 0275757..c06d1e7 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -719,6 +719,7 @@ void shader_core_ctx::writeback() m_last_inst_gpu_sim_cycle = gpu_sim_cycle; m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle; m_gpu->gpu_sim_insn += pipe_reg->active_count(); + pipe_reg->completed(gpu_tot_sim_cycle + gpu_sim_cycle); pipe_reg->clear(); } } @@ -945,6 +946,7 @@ void ldst_unit::writeback() // process next instruction that is going to writeback if( !m_next_wb.empty() ) { if( m_operand_collector->writeback(m_next_wb) ) { + bool insn_completed = false; for( unsigned r=0; r < 4; r++ ) { if( m_next_wb.out[r] > 0 ) { if( m_next_wb.space.get_type() != shared_space ) { @@ -955,14 +957,19 @@ void ldst_unit::writeback() m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] ); m_stats->m_num_sim_insn[m_sid]++; m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count(); + insn_completed = true; } } else { // shared m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] ); m_stats->m_num_sim_insn[m_sid]++; m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count(); + insn_completed = true; } } } + if( insn_completed ) { + m_next_wb.completed( gpu_tot_sim_cycle + gpu_sim_cycle ); + } m_next_wb.clear(); m_last_inst_gpu_sim_cycle = gpu_sim_cycle; m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle; @@ -1103,6 +1110,7 @@ void ldst_unit::cycle() } if( !pending_requests ) { m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count(); + m_dispatch_reg->completed(gpu_tot_sim_cycle + gpu_sim_cycle); m_scoreboard->releaseRegisters(m_dispatch_reg); m_stats->m_num_sim_insn[m_sid]++; } @@ -1113,6 +1121,7 @@ void ldst_unit::cycle() // stores exit pipeline here m_core->dec_inst_in_pipeline(warp_id); m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count(); + m_dispatch_reg->completed(gpu_tot_sim_cycle + gpu_sim_cycle); m_dispatch_reg->clear(); m_stats->m_num_sim_insn[m_sid]++; } |