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authorWilson Fung <[email protected]>2012-02-22 05:52:04 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:19:03 -0700
commit14c9cd2ccd09e3f1ce8b6a4659556bbb41b971fb (patch)
treecbce5f9fd9cd0a00322d6843a17411e987473319 /src/gpgpu-sim
parentf14d1687d360a9a9007eacec680a4a71cf9bc76b (diff)
Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
Diffstat (limited to 'src/gpgpu-sim')
-rw-r--r--src/gpgpu-sim/gpu-sim.cc3
-rw-r--r--src/gpgpu-sim/shader.cc10
-rw-r--r--src/gpgpu-sim/shader.h3
3 files changed, 14 insertions, 2 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 3200c9c..bd77c7b 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -236,6 +236,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp,
"Max number of instructions that can be issued per warp in one cycle by scheduler",
"2");
+ option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order,
+ "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)",
+ "1");
}
void gpgpu_sim_config::reg_options(option_parser_t opp)
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 742d3c9..060dd07 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -2046,13 +2046,19 @@ simt_core_cluster::simt_core_cluster( class gpgpu_sim *gpu,
for( unsigned i=0; i < config->n_simt_cores_per_cluster; i++ ) {
unsigned sid = m_config->cid_to_sid(i,m_cluster_id);
m_core[i] = new shader_core_ctx(gpu,this,sid,m_cluster_id,config,mem_config,stats);
+ m_core_sim_order.push_back(i);
}
}
void simt_core_cluster::core_cycle()
{
- for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ )
- m_core[i]->cycle();
+ for( std::list<unsigned>::iterator it = m_core_sim_order.begin(); it != m_core_sim_order.end(); ++it ) {
+ m_core[*it]->cycle();
+ }
+
+ if (m_config->simt_core_sim_order == 1) {
+ m_core_sim_order.splice(m_core_sim_order.end(), m_core_sim_order, m_core_sim_order.begin());
+ }
}
void simt_core_cluster::reinit()
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 1d86f02..759a58b 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -985,6 +985,8 @@ struct shader_core_config : public core_config
unsigned n_simt_clusters;
unsigned n_simt_ejection_buffer_size;
unsigned ldst_unit_response_queue_size;
+
+ int simt_core_sim_order;
unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; }
};
@@ -1275,6 +1277,7 @@ private:
shader_core_ctx **m_core;
unsigned m_cta_issue_next_core;
+ std::list<unsigned> m_core_sim_order;
std::list<mem_fetch*> m_response_fifo;
};