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authoraamir <[email protected]>2018-09-09 15:10:06 -0700
committeraamir <[email protected]>2018-09-09 15:10:06 -0700
commit7a77d951e6a900d61436df12826bb677aeaee6e6 (patch)
treec60e6ad27d4f4da273fdd8ceeae633b17e0e0273 /src/gpgpu-sim
parent242f3fd369f6ea3f0e808dd5d6446a294e63d9aa (diff)
minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED
Diffstat (limited to 'src/gpgpu-sim')
-rw-r--r--src/gpgpu-sim/shader.cc2
-rw-r--r--src/gpgpu-sim/shader.h8
2 files changed, 9 insertions, 1 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 6f11ad9..5e80fb1 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -920,7 +920,7 @@ void scheduler_unit::cycle()
ready_inst = true;
const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
assert( warp(warp_id).inst_in_pipeline() );
- if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
+ if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)||(pI->op ==VP_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) ||(pI->op==VP_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
if( m_mem_out->has_free() ) {
m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
issued++;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index d292d56..d9558b0 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1116,7 +1116,11 @@ public:
switch(inst.op) {
case SFU_OP: return false;
case LOAD_OP: return false;
+ case TENSOR_CORE_LOAD_OP: return false;
+ case VP_LOAD_OP: return false;
case STORE_OP: return false;
+ case TENSOR_CORE_STORE_OP: return false;
+ case VP_STORE_OP: return false;
case MEMORY_BARRIER_OP: return false;
default: break;
}
@@ -1158,7 +1162,11 @@ public:
{
switch(inst.op) {
case LOAD_OP: break;
+ case TENSOR_CORE_LOAD_OP: break;
+ case VP_LOAD_OP: break;
case STORE_OP: break;
+ case TENSOR_CORE_STORE_OP: break;
+ case VP_STORE_OP: break;
case MEMORY_BARRIER_OP: break;
default: return false;
}