adding texture cache model with fragment fifo for latency hiding

passing CUDA 3.1 regression

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]

1 files changed, 1 insertions, 1 deletions

diff --git a/src/intersim/interconnect_interface.cpp b/src/intersim/interconnect_interface.cpp
index b838dcf..40cf00d 100644
--- a/src/intersim/interconnect_interface.cpp
+++ b/src/intersim/interconnect_interface.cpp
@@ -467,7 +467,7 @@ void init_interconnect (char* config_file,
    if (icnt_config.GetInt("input_buf_size")) {
       input_buffer_capacity = icnt_config.GetInt("input_buf_size");
    } else {
-      input_buffer_capacity = 8;
+      input_buffer_capacity = 9;
    }
    create_buf(traffic[0]->_dests,input_buffer_capacity,icnt_config.GetInt( "num_vcs" )); 
    MATLAB_OUTPUT        = icnt_config.GetInt("MATLAB_OUTPUT");