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| author | Ali Bakhoda <[email protected]> | 2011-10-04 14:40:52 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:18:23 -0700 |
| commit | 6f64b0527dd7f8be12c17ab2b73e7bc5d9c8def8 (patch) | |
| tree | 3bf4125ce0173846cac25656a65192bd60ee371f /src/intersim/misc_utils.hpp | |
| parent | 39fde1bdd52080391a7083536b22a3ea9a686dcf (diff) | |
Ejection from the interface buffer between interconnet and L2 happens in L2 clock domain instead of ICNT clock domain.
Note: if NOT having an L2 cache is supported in later versions of this branch then this ejection needs to happen in DRAM clock domain when L2 is disabled.
cuda regression tests pass
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10501]
Diffstat (limited to 'src/intersim/misc_utils.hpp')
0 files changed, 0 insertions, 0 deletions