diff options
| author | Mahmoud <[email protected]> | 2019-11-21 01:35:38 -0500 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-11-21 01:35:38 -0500 |
| commit | 1353e4322328f369bd4c23bf228790f34984d860 (patch) | |
| tree | 65789881dae4ec44389c7478ac3c5f92440d83b8 /src | |
| parent | 689316eff10035a1171e6b4917ce0616ecb3e938 (diff) | |
fixing the access alignment in trace-driven mode
Diffstat (limited to 'src')
| -rw-r--r-- | src/abstract_hardware_model.cc | 21 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 4 |
2 files changed, 22 insertions, 3 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index fa5bca2..3d3d2f3 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -536,13 +536,30 @@ void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_ transaction_info &info = subwarp_transactions[block_address]; // can only write to one segment - assert(block_address == line_size_based_tag_func(addr+data_size_coales-1,segment_size)); + //it seems like in trace driven, a thread can write to more than one segment + //assert(block_address == line_size_based_tag_func(addr+data_size_coales-1,segment_size)); info.chunks.set(chunk); info.active.set(thread); unsigned idx = (addr&127); for( unsigned i=0; i < data_size_coales; i++ ) - info.bytes.set(idx+i); + if((idx+i) < MAX_MEMORY_ACCESS_SIZE) + info.bytes.set(idx+i); + + //it seems like in trace driven, a thread can write to more than one segment + //handle this special case + if(block_address != line_size_based_tag_func(addr+data_size_coales-1,segment_size)) { + addr = addr+data_size_coales-1; + unsigned block_address = line_size_based_tag_func(addr,segment_size); + unsigned chunk = (addr&127)/32; + transaction_info &info = subwarp_transactions[block_address]; + info.chunks.set(chunk); + info.active.set(thread); + unsigned idx = (addr&127); + for( unsigned i=0; i < data_size_coales; i++ ) + if((idx+i) < MAX_MEMORY_ACCESS_SIZE) + info.bytes.set(idx+i); + } } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index de6d975..23050d3 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1881,7 +1881,9 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea return true; if( inst.active_count() == 0 ) return true; - assert( !inst.accessq_empty() ); + if( inst.accessq_empty() ) + return true; + mem_stage_stall_type stall_cond = NO_RC_FAIL; const mem_access_t &access = inst.accessq_back(); |