Fixed GDDR5 parameters in Fermi config:

  - Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
  - Decreased the DRAM clock to 924MHz from 1848MHz.
  - Corrected CAS Latency and Write Latency in the timing constraints.
  - Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]

1 files changed, 1 insertions, 1 deletions

diff --git a/version b/version
index f4afe4f..da8015d 100644
--- a/version
+++ b/version
@@ -1,2 +1,2 @@
 const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 3.1.0+edits (development branch)";
-const char *g_gpgpusim_build_string   = "$Change: 12865 $";
+const char *g_gpgpusim_build_string   = "$Change: 13138 $";