diff options
| -rw-r--r-- | CHANGES | 5 | ||||
| -rw-r--r-- | src/gpgpu-sim/dram.cc | 18 | ||||
| -rw-r--r-- | src/gpgpu-sim/dram_sched.cc | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 5 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 5 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_latency_stat.cc | 8 |
6 files changed, 25 insertions, 18 deletions
@@ -12,7 +12,10 @@ Version 3.2.0+edits (development branch) versus 3.2.0 - Fixed L2 Writeback bug caused by using the memory partition address for both the cache set index generation and for storing tag/block address. Caused writebacks from the L2 to have a different address than the original - memory request. + memory request. + - For the clarity of the simulator might be improved by the following changes: + 1. Renaming '-gpgpu_dram_sched_queue_size' to '-gpgpu_frfcfs_dram_sched_queue_size' + 2. Updating the output not print out max and avg size statistics for the DRAM access scheduler queue if it is a FIFO. Version 3.2.0 versus 3.1.2 - Added GPUWattch GPGPU power model based on McPAT 0.8beta. diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 35b1d55..f28db2f 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -77,7 +77,7 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m prio = 0; rwq = new fifo_pipeline<dram_req_t>("rwq",m_config->CL,m_config->CL+1); mrqq = new fifo_pipeline<dram_req_t>("mrqq",0,2); - returnq = new fifo_pipeline<mem_fetch>("dramreturnq",0,m_config->gpgpu_dram_sched_queue_size); + returnq = new fifo_pipeline<mem_fetch>("dramreturnq",0,m_config->gpgpu_dram_return_queue_size==0?1024:m_config->gpgpu_dram_return_queue_size); m_frfcfs_scheduler = NULL; if ( m_config->scheduler_type == DRAM_FRFCFS ) m_frfcfs_scheduler = new frfcfs_scheduler(m_config,this,stats); @@ -117,12 +117,11 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m bool dram_t::full() const { - if( m_config->gpgpu_dram_sched_queue_size == 0 ) - return false; - if( m_config->scheduler_type == DRAM_FRFCFS ) - return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_dram_sched_queue_size; - else - return mrqq->full(); + if(m_config->scheduler_type == DRAM_FRFCFS ){ + if(m_config->gpgpu_frfcfs_dram_sched_queue_size == 0 ) return false; + return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; + } + else return mrqq->full(); } unsigned dram_t::que_length() const @@ -143,7 +142,7 @@ bool dram_t::returnq_full() const unsigned int dram_t::queue_limit() const { - return m_config->gpgpu_dram_sched_queue_size; + return m_config->gpgpu_frfcfs_dram_sched_queue_size; } @@ -448,7 +447,8 @@ void dram_t::print( FILE* simFile) const fprintf(simFile, "\ndram_eff_bins:"); for (i=0;i<10;i++) fprintf(simFile, " %d", dram_eff_bins[i]); fprintf(simFile, "\n"); - fprintf(simFile, "mrqq: max=%d avg=%g\n", max_mrqs, (float)ave_mrqs/n_cmd); + if(m_config->scheduler_type== DRAM_FRFCFS) + fprintf(simFile, "mrqq: max=%d avg=%g\n", max_mrqs, (float)ave_mrqs/n_cmd); } void dram_t::visualize() const diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 2f991c1..8303e86 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -129,7 +129,7 @@ void dram_t::scheduler_frfcfs() { unsigned mrq_latency; frfcfs_scheduler *sched = m_frfcfs_scheduler; - while ( !mrqq->empty() && (!m_config->gpgpu_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_dram_sched_queue_size)) { + while ( !mrqq->empty() && (!m_config->gpgpu_frfcfs_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_frfcfs_dram_sched_queue_size)) { dram_req_t *req = mrqq->pop(); // Power stats diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index ff5427a..3fa1d75 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -164,7 +164,10 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_memlatency_stat", OPT_INT32, &gpgpu_memlatency_stat, "track and display latency statistics 0x2 enables MC, 0x4 enables queue logs", "0"); - option_parser_register(opp, "-gpgpu_dram_sched_queue_size", OPT_INT32, &gpgpu_dram_sched_queue_size, + option_parser_register(opp, "-gpgpu_frfcfs_dram_sched_queue_size", OPT_INT32, &gpgpu_frfcfs_dram_sched_queue_size, + "0 = unlimited (default); # entries per chip", + "0"); + option_parser_register(opp, "-gpgpu_dram_return_queue_size", OPT_INT32, &gpgpu_dram_return_queue_size, "0 = unlimited (default); # entries per chip", "0"); option_parser_register(opp, "-gpgpu_dram_buswidth", OPT_UINT32, &busW, diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 6e5c3f0..e121030 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -215,7 +215,8 @@ struct memory_config { char *gpgpu_dram_timing_opt; char *gpgpu_L2_queue_config; bool l2_ideal; - unsigned gpgpu_dram_sched_queue_size; + unsigned gpgpu_frfcfs_dram_sched_queue_size; + unsigned gpgpu_dram_return_queue_size; enum dram_ctrl_t scheduler_type; bool gpgpu_memlatency_stat; unsigned m_n_mem; @@ -327,7 +328,7 @@ private: bool gpgpu_flush_l1_cache; bool gpgpu_flush_l2_cache; bool gpu_deadlock_detect; - int gpgpu_dram_sched_queue_size; + int gpgpu_frfcfs_dram_sched_queue_size; int gpgpu_cflog_interval; char * gpgpu_clock_domains; unsigned max_concurrent_kernel; diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index b86c652..7324033 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -94,8 +94,8 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf bankreads = (unsigned int***) calloc(n_shader, sizeof(unsigned int**)); bankwrites = (unsigned int***) calloc(n_shader, sizeof(unsigned int**)); num_MCBs_accessed = (unsigned int*) calloc(mem_config->m_n_mem*mem_config->nbk, sizeof(unsigned int)); - if (mem_config->gpgpu_dram_sched_queue_size) { - position_of_mrq_chosen = (unsigned int*) calloc(mem_config->gpgpu_dram_sched_queue_size, sizeof(unsigned int)); + if (mem_config->gpgpu_frfcfs_dram_sched_queue_size) { + position_of_mrq_chosen = (unsigned int*) calloc(mem_config->gpgpu_frfcfs_dram_sched_queue_size, sizeof(unsigned int)); } else position_of_mrq_chosen = (unsigned int*) calloc(1024, sizeof(unsigned int)); for (i=0;i<n_shader ;i++ ) { @@ -449,10 +449,10 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) printf("\nposition of mrq chosen\n"); - if (!m_memory_config->gpgpu_dram_sched_queue_size) + if (!m_memory_config->gpgpu_frfcfs_dram_sched_queue_size) j = 1024; else - j = m_memory_config->gpgpu_dram_sched_queue_size; + j = m_memory_config->gpgpu_frfcfs_dram_sched_queue_size; k=0;l=0; for (i=0;i< j; i++ ) { printf("%d\t", position_of_mrq_chosen[i]); |