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diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config
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-# This config models the Pascal GP102 (GeForceGTX 1080Ti)
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 11
--gpgpu_n_sub_partition_per_mchannel 2 
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 1,2,1,1,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
--gpgpu_shmem_size 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
--gpgpu_cache:dl2_texture_only 0 
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
-# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes 
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4  # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Pascal has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-