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-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config5
-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config4
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config7
-rw-r--r--configs/tested-cfgs/SM6_TITANX/trace.config4
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/gpgpusim.config8
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/trace.config5
-rw-r--r--configs/tested-cfgs/SM7_QV100/gpgpusim.config8
-rw-r--r--configs/tested-cfgs/SM7_QV100/trace.config6
-rw-r--r--configs/tested-cfgs/SM7_TITANV/gpgpusim.config8
-rw-r--r--configs/tested-cfgs/SM7_TITANV/trace.config6
10 files changed, 25 insertions, 36 deletions
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
index 9d0862a..b173dd0 100644
--- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
@@ -67,11 +67,6 @@
-ptx_opcode_initiation_sfu 2
-ptx_opcode_latency_sfu 200
--trace_opcode_latency_initiation_int 4,1
--trace_opcode_latency_initiation_sp 4,1
--trace_opcode_latency_initiation_dp 20,2
--trace_opcode_latency_initiation_sfu 200,2
-
# enable operand collector
-gpgpu_operand_collector_num_units_sp 12
-gpgpu_operand_collector_num_units_sfu 6
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config
new file mode 100644
index 0000000..4c80036
--- /dev/null
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config
@@ -0,0 +1,4 @@
+-trace_opcode_latency_initiation_int 4,1
+-trace_opcode_latency_initiation_sp 4,1
+-trace_opcode_latency_initiation_dp 20,2
+-trace_opcode_latency_initiation_sfu 200,2
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index a686238..ce6f745 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -22,8 +22,6 @@
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
-# SASS trace-driven mode execution
-#-trace_driven_mode 1
# high level architecture configuration
-gpgpu_n_clusters 28
@@ -66,11 +64,6 @@
-ptx_opcode_initiation_sfu 4
-ptx_opcode_latency_sfu 20
--trace_opcode_latency_initiation_int 4,1
--trace_opcode_latency_initiation_sp 4,1
--trace_opcode_latency_initiation_dp 20,8
--trace_opcode_latency_initiation_sfu 20,4
-
# in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs
-gpgpu_sub_core_model 1
# enable operand collector
diff --git a/configs/tested-cfgs/SM6_TITANX/trace.config b/configs/tested-cfgs/SM6_TITANX/trace.config
new file mode 100644
index 0000000..88bcdc0
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/trace.config
@@ -0,0 +1,4 @@
+-trace_opcode_latency_initiation_int 4,1
+-trace_opcode_latency_initiation_sp 4,1
+-trace_opcode_latency_initiation_dp 20,8
+-trace_opcode_latency_initiation_sfu 20,4
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index 5d23d1a..8a4be23 100644
--- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -22,8 +22,6 @@
# PTX execution-driven
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
-# SASS trace-driven mode execution
-#-trace_driven_mode 1
# high level architecture configuration
-gpgpu_n_clusters 30
@@ -72,12 +70,6 @@
-ptx_opcode_latency_tesnor 64
-ptx_opcode_initiation_tensor 64
--trace_opcode_latency_initiation_int 4,2
--trace_opcode_latency_initiation_sp 4,2
--trace_opcode_latency_initiation_dp 8,4
--trace_opcode_latency_initiation_sfu 20,8
--trace_opcode_latency_initiation_tensor 8,4
-
# Turing has four schedulers per core
-gpgpu_num_sched_per_core 4
# Greedy then oldest scheduler
diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config
new file mode 100644
index 0000000..41987cf
--- /dev/null
+++ b/configs/tested-cfgs/SM75_RTX2060/trace.config
@@ -0,0 +1,5 @@
+-trace_opcode_latency_initiation_int 4,2
+-trace_opcode_latency_initiation_sp 4,2
+-trace_opcode_latency_initiation_dp 8,4
+-trace_opcode_latency_initiation_sfu 20,8
+-trace_opcode_latency_initiation_tensor 8,4
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 5856e5d..c31c060 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -28,8 +28,6 @@
# PTX execution-driven
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
-# SASS trace-driven mode support
-#-trace_driven_mode 1
# high level architecture configuration
-gpgpu_n_clusters 80
@@ -79,12 +77,6 @@
-ptx_opcode_latency_tesnor 64
-ptx_opcode_initiation_tensor 64
--trace_opcode_latency_initiation_int 4,2
--trace_opcode_latency_initiation_sp 4,2
--trace_opcode_latency_initiation_dp 8,4
--trace_opcode_latency_initiation_sfu 20,8
--trace_opcode_latency_initiation_tensor 8,4
-
# Volta has sub core model, in which each scheduler has its own register file and EUs
# i.e. schedulers are isolated
-gpgpu_sub_core_model 1
diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config
new file mode 100644
index 0000000..04ac009
--- /dev/null
+++ b/configs/tested-cfgs/SM7_QV100/trace.config
@@ -0,0 +1,6 @@
+-trace_opcode_latency_initiation_int 4,2
+-trace_opcode_latency_initiation_sp 4,2
+-trace_opcode_latency_initiation_dp 8,4
+-trace_opcode_latency_initiation_sfu 20,8
+-trace_opcode_latency_initiation_tensor 8,4
+
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index b5f88ce..ef28dd8 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -26,8 +26,6 @@
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
-# SASS trace-driven mode support
-#-trace_driven_mode 1
# high level architecture configuration
-gpgpu_n_clusters 40
@@ -81,12 +79,6 @@
-ptx_opcode_latency_tesnor 64
-ptx_opcode_initiation_tensor 64
--trace_opcode_latency_initiation_int 4,2
--trace_opcode_latency_initiation_sp 4,2
--trace_opcode_latency_initiation_dp 8,4
--trace_opcode_latency_initiation_sfu 20,8
--trace_opcode_latency_initiation_tensor 8,4
-
# Volta has sub core model, in which each scheduler has its own register file and EUs
# i.e. schedulers are isolated
-gpgpu_sub_core_model 1
diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config
new file mode 100644
index 0000000..04ac009
--- /dev/null
+++ b/configs/tested-cfgs/SM7_TITANV/trace.config
@@ -0,0 +1,6 @@
+-trace_opcode_latency_initiation_int 4,2
+-trace_opcode_latency_initiation_sp 4,2
+-trace_opcode_latency_initiation_dp 8,4
+-trace_opcode_latency_initiation_sfu 20,8
+-trace_opcode_latency_initiation_tensor 8,4
+
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:45:32 +0000