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-rw-r--r--src/cuda-sim/cuda-sim.cc204
1 files changed, 136 insertions, 68 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 71f0703..680ce79 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -1,19 +1,21 @@
-// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung,
-// George L. Yuan, Jimmy Kwa
-// The University of British Columbia
+// Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung,
+// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
-// Redistributions of source code must retain the above copyright notice, this
-// list of conditions and the following disclaimer.
-// Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution. Neither the name of
-// The University of British Columbia nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
+// 1. Redistributions of source code must retain the above copyright notice, this
+// list of conditions and the following disclaimer;
+// 2. Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution;
+// 3. Neither the names of The University of British Columbia, Northwestern
+// University nor the names of their contributors may be used to
+// endorse or promote products derived from this software without specific
+// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -588,65 +590,119 @@ void ptx_instruction::set_fp_or_int_archop() {
oprnd_type = INT_OP;
}
}
-void ptx_instruction::set_mul_div_or_other_archop() {
- sp_op = OTHER_OP;
- if ((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) &&
- (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) &&
- (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) &&
- (m_opcode != CALL_OP)) {
- if (get_type() == F32_TYPE || get_type() == F64_TYPE ||
- get_type() == FF64_TYPE) {
- switch (get_opcode()) {
- case MUL_OP:
- case MAD_OP:
- sp_op = FP_MUL_OP;
- break;
- case DIV_OP:
- sp_op = FP_DIV_OP;
- break;
- case LG2_OP:
- sp_op = FP_LG_OP;
- break;
- case RSQRT_OP:
- case SQRT_OP:
- sp_op = FP_SQRT_OP;
- break;
- case RCP_OP:
- sp_op = FP_DIV_OP;
- break;
- case SIN_OP:
- case COS_OP:
- sp_op = FP_SIN_OP;
- break;
- case EX2_OP:
- sp_op = FP_EXP_OP;
- break;
- default:
- if ((op == ALU_OP) || (op == TENSOR_CORE_OP)) sp_op = FP__OP;
- break;
+
+void ptx_instruction::set_mul_div_or_other_archop(){
+ sp_op=OTHER_OP;
+ if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){
+ if(get_type() == F64_TYPE || get_type() == FF64_TYPE){
+ switch(get_opcode()){
+ case MUL_OP:
+ case MAD_OP:
+ case FMA_OP:
+ sp_op=DP_MUL_OP;
+ break;
+ case DIV_OP:
+ case REM_OP:
+ sp_op=DP_DIV_OP;
+ break;
+ case RCP_OP:
+ sp_op=DP_DIV_OP;
+ break;
+ case LG2_OP:
+ sp_op=FP_LG_OP;
+ break;
+ case RSQRT_OP:
+ case SQRT_OP:
+ sp_op=FP_SQRT_OP;
+ break;
+ case SIN_OP:
+ case COS_OP:
+ sp_op=FP_SIN_OP;
+ break;
+ case EX2_OP:
+ sp_op=FP_EXP_OP;
+ break;
+ case MMA_OP:
+ sp_op=TENSOR__OP;
+ break;
+ case TEX_OP:
+ sp_op=TEX__OP;
+ break;
+ default:
+ if((op==DP_OP) || (op==ALU_OP))
+ sp_op=DP___OP;
+ break;
+ }
}
- } else {
- switch (get_opcode()) {
- case MUL24_OP:
- case MAD24_OP:
- sp_op = INT_MUL24_OP;
- break;
- case MUL_OP:
- case MAD_OP:
- if (get_type() == U32_TYPE || get_type() == S32_TYPE ||
- get_type() == B32_TYPE)
- sp_op = INT_MUL32_OP;
- else
- sp_op = INT_MUL_OP;
- break;
- case DIV_OP:
- sp_op = INT_DIV_OP;
- break;
- default:
- if ((op == ALU_OP)) sp_op = INT__OP;
- break;
+ else if(get_type()==F16_TYPE || get_type()==F32_TYPE){
+ switch(get_opcode()){
+ case MUL_OP:
+ case MAD_OP:
+ case FMA_OP:
+ sp_op=FP_MUL_OP;
+ break;
+ case DIV_OP:
+ case REM_OP:
+ sp_op=FP_DIV_OP;
+ break;
+ case RCP_OP:
+ sp_op=FP_DIV_OP;
+ break;
+ case LG2_OP:
+ sp_op=FP_LG_OP;
+ break;
+ case RSQRT_OP:
+ case SQRT_OP:
+ sp_op=FP_SQRT_OP;
+ break;
+ case SIN_OP:
+ case COS_OP:
+ sp_op=FP_SIN_OP;
+ break;
+ case EX2_OP:
+ sp_op=FP_EXP_OP;
+ break;
+ case MMA_OP:
+ sp_op=TENSOR__OP;
+ break;
+ case TEX_OP:
+ sp_op=TEX__OP;
+ break;
+ default:
+ if((op==SP_OP) || (op==ALU_OP))
+ sp_op=FP__OP;
+ break;
+ }
+ }else {
+ switch(get_opcode()){
+ case MUL24_OP:
+ case MAD24_OP:
+ sp_op=INT_MUL24_OP;
+ break;
+ case MUL_OP:
+ case MAD_OP:
+ case FMA_OP:
+ if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE)
+ sp_op=INT_MUL32_OP;
+ else
+ sp_op=INT_MUL_OP;
+ break;
+ case DIV_OP:
+ case REM_OP:
+ sp_op=INT_DIV_OP;
+ break;
+ case MMA_OP:
+ sp_op=TENSOR__OP;
+ break;
+ case TEX_OP:
+ sp_op=TEX__OP;
+ break;
+ default:
+ if((op==INTP_OP) || (op==ALU_OP))
+ sp_op=INT__OP;
+ break;
+ }
}
- }
}
}
@@ -880,6 +936,7 @@ void ptx_instruction::set_opcode_and_latency() {
case MAD_OP:
case MADC_OP:
case MADP_OP:
+ case FMA_OP:
// MAD latency
switch (get_type()) {
case F32_TYPE:
@@ -903,7 +960,18 @@ void ptx_instruction::set_opcode_and_latency() {
break;
}
break;
+ case MUL24_OP: //MUL24 is performed on mul32 units (with additional instructions for bitmasking) on devices with compute capability >1.x
+ latency = int_latency[2]+1;
+ initiation_interval = int_init[2]+1;
+ op = INTP_OP;
+ break;
+ case MAD24_OP:
+ latency = int_latency[3]+1;
+ initiation_interval = int_init[3]+1;
+ op = INTP_OP;
+ break;
case DIV_OP:
+ case REM_OP:
// Floating point only
op = SFU_OP;
switch (get_type()) {
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:32:55 +0000