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-rw-r--r--src/gpgpu-sim/shader.cc331
1 files changed, 176 insertions, 155 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 855aa1c..9fe4c09 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1,18 +1,19 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda,
-// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas,
-// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
-// The University of British Columbia, Northwestern University, Purdue University
-// All rights reserved.
+// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos
+// Hardavellas, Mahmoud Khairy, Junrui Pan, Timothy G. Rogers The University of
+// British Columbia, Northwestern University, Purdue University All rights
+// reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
-// 1. Redistributions of source code must retain the above copyright notice, this
+// 1. Redistributions of source code must retain the above copyright notice,
+// this
// list of conditions and the following disclaimer;
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution;
-// 3. Neither the names of The University of British Columbia, Northwestern
+// 3. Neither the names of The University of British Columbia, Northwestern
// University nor the names of their contributors may be used to
// endorse or promote products derived from this software without specific
// prior written permission.
@@ -187,20 +188,16 @@ void shader_core_ctx::create_schedulers() {
// must currently occur after all inputs have been initialized.
std::string sched_config = m_config->gpgpu_scheduler_string;
const concrete_scheduler scheduler =
- sched_config.find("lrr") != std::string::npos
- ? CONCRETE_SCHEDULER_LRR
- : sched_config.find("two_level_active") != std::string::npos
- ? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE
- : sched_config.find("gto") != std::string::npos
- ? CONCRETE_SCHEDULER_GTO
- : sched_config.find("rrr") != std::string::npos
- ? CONCRETE_SCHEDULER_RRR
- : sched_config.find("old") != std::string::npos
- ? CONCRETE_SCHEDULER_OLDEST_FIRST
- : sched_config.find("warp_limiting") !=
- std::string::npos
- ? CONCRETE_SCHEDULER_WARP_LIMITING
- : NUM_CONCRETE_SCHEDULERS;
+ sched_config.find("lrr") != std::string::npos ? CONCRETE_SCHEDULER_LRR
+ : sched_config.find("two_level_active") != std::string::npos
+ ? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE
+ : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO
+ : sched_config.find("rrr") != std::string::npos ? CONCRETE_SCHEDULER_RRR
+ : sched_config.find("old") != std::string::npos
+ ? CONCRETE_SCHEDULER_OLDEST_FIRST
+ : sched_config.find("warp_limiting") != std::string::npos
+ ? CONCRETE_SCHEDULER_WARP_LIMITING
+ : NUM_CONCRETE_SCHEDULERS;
assert(scheduler != NUM_CONCRETE_SCHEDULERS);
for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) {
@@ -487,8 +484,8 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu,
m_sid = shader_id;
m_tpc = tpc_id;
- if(get_gpu()->get_config().g_power_simulation_enabled){
- scaling_coeffs = get_gpu()->get_scaling_coeffs();
+ if (get_gpu()->get_config().g_power_simulation_enabled) {
+ scaling_coeffs = get_gpu()->get_scaling_coeffs();
}
m_last_inst_gpu_sim_cycle = 0;
@@ -641,7 +638,8 @@ void shader_core_stats::print(FILE *fout) const {
fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn);
fprintf(fout, "gpgpu_n_shmem_bkconflict = %d\n", gpgpu_n_shmem_bkconflict);
- fprintf(fout, "gpgpu_n_l1cache_bkconflict = %d\n", gpgpu_n_l1cache_bkconflict);
+ fprintf(fout, "gpgpu_n_l1cache_bkconflict = %d\n",
+ gpgpu_n_l1cache_bkconflict);
fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n",
gpgpu_n_intrawarp_mshr_merge);
@@ -893,7 +891,9 @@ void shader_core_ctx::decode() {
m_warp[m_inst_fetch_buffer.m_warp_id]->inc_inst_in_pipeline();
if (pI1) {
m_stats->m_num_decoded_insn[m_sid]++;
- if ((pI1->oprnd_type == INT_OP) || (pI1->oprnd_type == UN_OP)) { //these counters get added up in mcPat to compute scheduler power
+ if ((pI1->oprnd_type == INT_OP) ||
+ (pI1->oprnd_type == UN_OP)) { // these counters get added up in mcPat
+ // to compute scheduler power
m_stats->m_num_INTdecoded_insn[m_sid]++;
} else if (pI1->oprnd_type == FP_OP) {
m_stats->m_num_FPdecoded_insn[m_sid]++;
@@ -904,7 +904,9 @@ void shader_core_ctx::decode() {
m_warp[m_inst_fetch_buffer.m_warp_id]->ibuffer_fill(1, pI2);
m_warp[m_inst_fetch_buffer.m_warp_id]->inc_inst_in_pipeline();
m_stats->m_num_decoded_insn[m_sid]++;
- if ((pI1->oprnd_type == INT_OP) || (pI1->oprnd_type == UN_OP)) { //these counters get added up in mcPat to compute scheduler power
+ if ((pI1->oprnd_type == INT_OP) ||
+ (pI1->oprnd_type == UN_OP)) { // these counters get added up in
+ // mcPat to compute scheduler power
m_stats->m_num_INTdecoded_insn[m_sid]++;
} else if (pI2->oprnd_type == FP_OP) {
m_stats->m_num_FPdecoded_insn[m_sid]++;
@@ -950,7 +952,8 @@ void shader_core_ctx::fetch() {
m_threadState[tid].m_active = false;
unsigned cta_id = m_warp[warp_id]->get_cta_id();
if (m_thread[tid] == NULL) {
- register_cta_thread_exit(cta_id, m_warp[warp_id]->get_kernel_info());
+ register_cta_thread_exit(cta_id,
+ m_warp[warp_id]->get_kernel_info());
} else {
register_cta_thread_exit(cta_id,
&(m_thread[tid]->get_kernel()));
@@ -987,11 +990,10 @@ void shader_core_ctx::fetch() {
m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle);
std::list<cache_event> events;
enum cache_request_status status;
- if (m_config->perfect_inst_const_cache){
+ if (m_config->perfect_inst_const_cache) {
status = HIT;
shader_cache_access_log(m_sid, INSTRUCTION, 0);
- }
- else
+ } else
status = m_L1I->access(
(new_addr_type)ppc, mf,
m_gpu->gpu_sim_cycle + m_gpu->gpu_tot_sim_cycle, events);
@@ -1050,14 +1052,13 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
if (next_inst->m_is_ldgsts) {
if (m_warp[warp_id]->m_ldgdepbar_buf.size() == ldgdepbar_id + 1) {
m_warp[warp_id]->m_ldgdepbar_buf[ldgdepbar_id].push_back(*next_inst);
- }
- else {
+ } else {
assert(m_warp[warp_id]->m_ldgdepbar_buf.size() < ldgdepbar_id + 1);
std::vector<warp_inst_t> l;
l.push_back(*next_inst);
m_warp[warp_id]->m_ldgdepbar_buf.push_back(l);
}
- // If the mask of the instruction is all 0, then the address is also 0,
+ // If the mask of the instruction is all 0, then the address is also 0,
// so that there's no need to check through the writeback
if (next_inst->get_active_mask() == 0) {
(m_warp[warp_id]->m_ldgdepbar_buf.back()).back().pc = -1;
@@ -1071,7 +1072,7 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
} else if (next_inst->op == MEMORY_BARRIER_OP) {
m_warp[warp_id]->set_membar();
- } else if (next_inst->m_is_ldgdepbar) { // Add for LDGDEPBAR
+ } else if (next_inst->m_is_ldgdepbar) { // Add for LDGDEPBAR
m_warp[warp_id]->m_ldgdepbar_id++;
// If there are no added LDGSTS, insert an empty vector
if (m_warp[warp_id]->m_ldgdepbar_buf.size() != ldgdepbar_id + 1) {
@@ -1082,16 +1083,20 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
} else if (next_inst->m_is_depbar) { // Add for DEPBAR
// Set to true immediately when a DEPBAR instruction is met
m_warp[warp_id]->m_waiting_ldgsts = true;
- m_warp[warp_id]->m_depbar_group = next_inst->m_depbar_group_no; // set in trace_driven.cc
+ m_warp[warp_id]->m_depbar_group =
+ next_inst->m_depbar_group_no; // set in trace_driven.cc
- // Record the last group that's possbily being monitored by this DEPBAR instr
+ // Record the last group that's possbily being monitored by this DEPBAR
+ // instr
m_warp[warp_id]->m_depbar_start_id = m_warp[warp_id]->m_ldgdepbar_id - 1;
-
- // Record the last group that's actually being monitored by this DEPBAR instr
- unsigned int end_group = m_warp[warp_id]->m_ldgdepbar_id - m_warp[warp_id]->m_depbar_group;
- // Check for the case that the LDGSTSs monitored have finished when encountering the
- // DEPBAR instruction
+ // Record the last group that's actually being monitored by this DEPBAR
+ // instr
+ unsigned int end_group =
+ m_warp[warp_id]->m_ldgdepbar_id - m_warp[warp_id]->m_depbar_group;
+
+ // Check for the case that the LDGSTSs monitored have finished when
+ // encountering the DEPBAR instruction
bool done_flag = true;
for (int i = 0; i < end_group; i++) {
for (int j = 0; j < m_warp[warp_id]->m_ldgdepbar_buf[i].size(); j++) {
@@ -1101,7 +1106,7 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
}
}
}
-
+
UpdateDEPBAR:
if (done_flag) {
if (m_warp[warp_id]->m_waiting_ldgsts) {
@@ -1184,11 +1189,12 @@ void scheduler_unit::order_rrr(
if (m_num_issued_last_cycle > 0 || warp(m_current_turn_warp).done_exit() ||
warp(m_current_turn_warp).waiting()) {
std::vector<shd_warp_t *>::const_iterator iter =
- (last_issued_from_input == input_list.end()) ?
- input_list.begin() : last_issued_from_input + 1;
+ (last_issued_from_input == input_list.end())
+ ? input_list.begin()
+ : last_issued_from_input + 1;
for (unsigned count = 0; count < num_warps_to_add; ++iter, ++count) {
if (iter == input_list.end()) {
- iter = input_list.begin();
+ iter = input_list.begin();
}
unsigned warp_id = (*iter)->get_warp_id();
if (!(*iter)->done_exit() && !(*iter)->waiting()) {
@@ -1854,33 +1860,38 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const {
// Add this function to unset depbar
void shader_core_ctx::unset_depbar(const warp_inst_t &inst) {
bool done_flag = true;
- unsigned int end_group = m_warp[inst.warp_id()]->m_depbar_start_id == 0 ?
- m_warp[inst.warp_id()]->m_ldgdepbar_buf.size() :
- (m_warp[inst.warp_id()]->m_depbar_start_id - m_warp[inst.warp_id()]->m_depbar_group + 1);
+ unsigned int end_group = m_warp[inst.warp_id()]->m_depbar_start_id == 0
+ ? m_warp[inst.warp_id()]->m_ldgdepbar_buf.size()
+ : (m_warp[inst.warp_id()]->m_depbar_start_id -
+ m_warp[inst.warp_id()]->m_depbar_group + 1);
- if (inst.m_is_ldgsts) {
+ if (inst.m_is_ldgsts) {
for (int i = 0; i < m_warp[inst.warp_id()]->m_ldgdepbar_buf.size(); i++) {
- for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); j++) {
+ for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size();
+ j++) {
if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc == inst.pc) {
- // Handle the case that same pc results in multiple LDGSTS instructions
- if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].get_addr(0) == inst.get_addr(0)) {
+ // Handle the case that same pc results in multiple LDGSTS
+ // instructions
+ if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].get_addr(0) ==
+ inst.get_addr(0)) {
m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc = -1;
goto DoneWB;
}
- }
+ }
}
}
DoneWB:
for (int i = 0; i < end_group; i++) {
- for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); j++) {
+ for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size();
+ j++) {
if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc != -1) {
done_flag = false;
goto UpdateDEPBAR;
}
}
}
-
+
UpdateDEPBAR:
if (done_flag) {
if (m_warp[inst.warp_id()]->m_waiting_ldgsts) {
@@ -2000,7 +2011,7 @@ mem_stage_stall_type ldst_unit::process_cache_access(
if (inst.is_load()) {
for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++)
if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]]--;
-
+
// release LDGSTS
if (inst.m_is_ldgsts) {
m_pending_ldgsts[inst.warp_id()][inst.pc][inst.get_addr(0)]--;
@@ -2139,8 +2150,12 @@ void ldst_unit::L1_latency_queue_cycle() {
// release LDGSTS
if (mf_next->get_inst().m_is_ldgsts) {
- m_pending_ldgsts[mf_next->get_inst().warp_id()][mf_next->get_inst().pc][mf_next->get_inst().get_addr(0)]--;
- if (m_pending_ldgsts[mf_next->get_inst().warp_id()][mf_next->get_inst().pc][mf_next->get_inst().get_addr(0)] == 0) {
+ m_pending_ldgsts[mf_next->get_inst().warp_id()]
+ [mf_next->get_inst().pc]
+ [mf_next->get_inst().get_addr(0)]--;
+ if (m_pending_ldgsts[mf_next->get_inst().warp_id()]
+ [mf_next->get_inst().pc]
+ [mf_next->get_inst().get_addr(0)] == 0) {
m_core->unset_depbar(mf_next->get_inst());
}
}
@@ -2207,7 +2222,8 @@ bool ldst_unit::constant_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail,
while (inst.accessq_count() > 0) inst.accessq_pop_back();
if (inst.is_load()) {
for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++)
- if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]] -= access_count;
+ if (inst.out[r] > 0)
+ m_pending_writes[inst.warp_id()][inst.out[r]] -= access_count;
}
} else {
fail = process_memory_access_queue(m_L1C, inst);
@@ -2395,7 +2411,7 @@ void sp_unit::active_lanes_in_pipeline() {
void dp_unit::active_lanes_in_pipeline() {
unsigned active_count = pipelined_simd_unit::get_active_lanes_in_pipeline();
assert(active_count <= m_core->get_config()->warp_size);
- //m_core->incspactivelanes_stat(active_count);
+ // m_core->incspactivelanes_stat(active_count);
m_core->incfuactivelanes_stat(active_count);
m_core->incfumemactivelanes_stat(active_count);
}
@@ -2527,9 +2543,9 @@ void pipelined_simd_unit::cycle() {
if (!m_dispatch_reg->dispatch_delay()) {
int start_stage =
m_dispatch_reg->latency - m_dispatch_reg->initiation_interval;
- if(m_pipeline_reg[start_stage]->empty()) {
- move_warp(m_pipeline_reg[start_stage], m_dispatch_reg);
- active_insts_in_pipeline++;
+ if (m_pipeline_reg[start_stage]->empty()) {
+ move_warp(m_pipeline_reg[start_stage], m_dispatch_reg);
+ active_insts_in_pipeline++;
}
}
}
@@ -2682,10 +2698,12 @@ void ldst_unit::writeback() {
m_next_wb.out[r]);
insn_completed = true;
}
- }
- else if (m_next_wb.m_is_ldgsts) { // for LDGSTS instructions where no output register is used
- m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc][m_next_wb.get_addr(0)]--;
- if (m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc][m_next_wb.get_addr(0)] == 0) {
+ } else if (m_next_wb.m_is_ldgsts) { // for LDGSTS instructions where no
+ // output register is used
+ m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc]
+ [m_next_wb.get_addr(0)]--;
+ if (m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc]
+ [m_next_wb.get_addr(0)] == 0) {
insn_completed = true;
}
break;
@@ -2923,7 +2941,8 @@ void ldst_unit::cycle() {
// release LDGSTS
if (m_dispatch_reg->m_is_ldgsts) {
// m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc][m_dispatch_reg->get_addr(0)]--;
- if (m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc][m_dispatch_reg->get_addr(0)] == 0) {
+ if (m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc]
+ [m_dispatch_reg->get_addr(0)] == 0) {
m_core->unset_depbar(*m_dispatch_reg);
}
}
@@ -3223,68 +3242,68 @@ void warp_inst_t::print(FILE *fout) const {
m_config->gpgpu_ctx->func_sim->ptx_print_insn(pc, fout);
fprintf(fout, "\n");
}
-void shader_core_ctx::incexecstat(warp_inst_t *&inst)
-{
- // Latency numbers for next operations are used to scale the power values
- // for special operations, according observations from microbenchmarking
- // TODO: put these numbers in the xml configuration
- if(get_gpu()->get_config().g_power_simulation_enabled){
- switch(inst->sp_op){
- case INT__OP:
- incialu_stat(inst->active_count(), scaling_coeffs->int_coeff);
- break;
- case INT_MUL_OP:
- incimul_stat(inst->active_count(), scaling_coeffs->int_mul_coeff);
- break;
- case INT_MUL24_OP:
- incimul24_stat(inst->active_count(), scaling_coeffs->int_mul24_coeff);
- break;
- case INT_MUL32_OP:
- incimul32_stat(inst->active_count(), scaling_coeffs->int_mul32_coeff);
- break;
- case INT_DIV_OP:
- incidiv_stat(inst->active_count(), scaling_coeffs->int_div_coeff);
- break;
- case FP__OP:
- incfpalu_stat(inst->active_count(),scaling_coeffs->fp_coeff);
- break;
- case FP_MUL_OP:
- incfpmul_stat(inst->active_count(), scaling_coeffs->fp_mul_coeff);
- break;
- case FP_DIV_OP:
- incfpdiv_stat(inst->active_count(), scaling_coeffs->fp_div_coeff);
- break;
- case DP___OP:
- incdpalu_stat(inst->active_count(), scaling_coeffs->dp_coeff);
- break;
- case DP_MUL_OP:
- incdpmul_stat(inst->active_count(), scaling_coeffs->dp_mul_coeff);
- break;
- case DP_DIV_OP:
- incdpdiv_stat(inst->active_count(), scaling_coeffs->dp_div_coeff);
- break;
- case FP_SQRT_OP:
- incsqrt_stat(inst->active_count(), scaling_coeffs->sqrt_coeff);
- break;
- case FP_LG_OP:
- inclog_stat(inst->active_count(), scaling_coeffs->log_coeff);
- break;
- case FP_SIN_OP:
- incsin_stat(inst->active_count(), scaling_coeffs->sin_coeff);
- break;
- case FP_EXP_OP:
- incexp_stat(inst->active_count(), scaling_coeffs->exp_coeff);
- break;
- case TENSOR__OP:
- inctensor_stat(inst->active_count(), scaling_coeffs->tensor_coeff);
- break;
- case TEX__OP:
- inctex_stat(inst->active_count(), scaling_coeffs->tex_coeff);
- break;
- default:
- break;
+void shader_core_ctx::incexecstat(warp_inst_t *&inst) {
+ // Latency numbers for next operations are used to scale the power values
+ // for special operations, according observations from microbenchmarking
+ // TODO: put these numbers in the xml configuration
+ if (get_gpu()->get_config().g_power_simulation_enabled) {
+ switch (inst->sp_op) {
+ case INT__OP:
+ incialu_stat(inst->active_count(), scaling_coeffs->int_coeff);
+ break;
+ case INT_MUL_OP:
+ incimul_stat(inst->active_count(), scaling_coeffs->int_mul_coeff);
+ break;
+ case INT_MUL24_OP:
+ incimul24_stat(inst->active_count(), scaling_coeffs->int_mul24_coeff);
+ break;
+ case INT_MUL32_OP:
+ incimul32_stat(inst->active_count(), scaling_coeffs->int_mul32_coeff);
+ break;
+ case INT_DIV_OP:
+ incidiv_stat(inst->active_count(), scaling_coeffs->int_div_coeff);
+ break;
+ case FP__OP:
+ incfpalu_stat(inst->active_count(), scaling_coeffs->fp_coeff);
+ break;
+ case FP_MUL_OP:
+ incfpmul_stat(inst->active_count(), scaling_coeffs->fp_mul_coeff);
+ break;
+ case FP_DIV_OP:
+ incfpdiv_stat(inst->active_count(), scaling_coeffs->fp_div_coeff);
+ break;
+ case DP___OP:
+ incdpalu_stat(inst->active_count(), scaling_coeffs->dp_coeff);
+ break;
+ case DP_MUL_OP:
+ incdpmul_stat(inst->active_count(), scaling_coeffs->dp_mul_coeff);
+ break;
+ case DP_DIV_OP:
+ incdpdiv_stat(inst->active_count(), scaling_coeffs->dp_div_coeff);
+ break;
+ case FP_SQRT_OP:
+ incsqrt_stat(inst->active_count(), scaling_coeffs->sqrt_coeff);
+ break;
+ case FP_LG_OP:
+ inclog_stat(inst->active_count(), scaling_coeffs->log_coeff);
+ break;
+ case FP_SIN_OP:
+ incsin_stat(inst->active_count(), scaling_coeffs->sin_coeff);
+ break;
+ case FP_EXP_OP:
+ incexp_stat(inst->active_count(), scaling_coeffs->exp_coeff);
+ break;
+ case TENSOR__OP:
+ inctensor_stat(inst->active_count(), scaling_coeffs->tensor_coeff);
+ break;
+ case TEX__OP:
+ inctex_stat(inst->active_count(), scaling_coeffs->tex_coeff);
+ break;
+ default:
+ break;
}
- if(inst->const_cache_operand) //warp has const address space load as one operand
+ if (inst->const_cache_operand) // warp has const address space load as one
+ // operand
inc_const_accesses(1);
}
}
@@ -4034,7 +4053,9 @@ void shader_core_ctx::get_icnt_power_stats(long &n_simt_to_mem,
n_mem_to_simt += m_stats->n_mem_to_simt[m_sid];
}
-kernel_info_t* shd_warp_t::get_kernel_info() const { return m_shader->get_kernel_info(); }
+kernel_info_t *shd_warp_t::get_kernel_info() const {
+ return m_shader->get_kernel_info();
+}
bool shd_warp_t::functional_done() const {
return get_n_completed() == m_warp_size;
@@ -4069,7 +4090,8 @@ bool shd_warp_t::waiting() {
void shd_warp_t::print(FILE *fout) const {
if (!done_exit()) {
- fprintf(fout, "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
+ fprintf(fout,
+ "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
m_warp_id, m_next_pc, (functional_done() ? 'f' : ' '),
(stores_done() ? 's' : ' '), (inst_in_pipeline() ? ' ' : 'i'),
(done_exit() ? 'e' : ' '), n_completed, m_inst_in_pipeline,
@@ -4156,18 +4178,18 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) {
unsigned cusPerSched = m_cu.size() / m_num_warp_scheds;
reg_id = j / cusPerSched;
}
- m_cu[j]->init(j, num_banks, shader->get_config(), this,
- sub_core_model, reg_id, m_num_banks_per_sched);
+ m_cu[j]->init(j, num_banks, shader->get_config(), this, sub_core_model,
+ reg_id, m_num_banks_per_sched);
}
for (unsigned j = 0; j < m_dispatch_units.size(); j++) {
- m_dispatch_units[j].init(sub_core_model,m_num_warp_scheds);
+ m_dispatch_units[j].init(sub_core_model, m_num_warp_scheds);
}
m_initialized = true;
}
unsigned register_bank(int regnum, int wid, unsigned num_banks,
- bool sub_core_model,
- unsigned banks_per_sched, unsigned sched_id) {
+ bool sub_core_model, unsigned banks_per_sched,
+ unsigned sched_id) {
int bank = regnum;
bank += wid;
if (sub_core_model) {
@@ -4186,14 +4208,13 @@ bool opndcoll_rfu_t::writeback(warp_inst_t &inst) {
int reg_num = inst.arch_reg.dst[op]; // this math needs to match that used
// in function_info::ptx_decode_inst
if (reg_num >= 0) { // valid register
- unsigned bank = register_bank(reg_num, inst.warp_id(), m_num_banks,
- sub_core_model,
- m_num_banks_per_sched, inst.get_schd_id());
+ unsigned bank =
+ register_bank(reg_num, inst.warp_id(), m_num_banks, sub_core_model,
+ m_num_banks_per_sched, inst.get_schd_id());
if (m_arbiter.bank_idle(bank)) {
m_arbiter.allocate_bank_for_write(
- bank,
- op_t(&inst, reg_num, m_num_banks, sub_core_model,
- m_num_banks_per_sched, inst.get_schd_id()));
+ bank, op_t(&inst, reg_num, m_num_banks, sub_core_model,
+ m_num_banks_per_sched, inst.get_schd_id()));
inst.arch_reg.dst[op] = -1;
} else {
return false;
@@ -4301,9 +4322,8 @@ void opndcoll_rfu_t::allocate_reads() {
const op_t &rr = *r;
unsigned reg = rr.get_reg();
unsigned wid = rr.get_wid();
- unsigned bank =
- register_bank(reg, wid, m_num_banks, sub_core_model,
- m_num_banks_per_sched, rr.get_sid());
+ unsigned bank = register_bank(reg, wid, m_num_banks, sub_core_model,
+ m_num_banks_per_sched, rr.get_sid());
m_arbiter.allocate_for_read(bank, rr);
read_ops[bank] = rr;
}
@@ -4353,10 +4373,12 @@ void opndcoll_rfu_t::collector_unit_t::dump(
}
}
-void opndcoll_rfu_t::collector_unit_t::init(
- unsigned n, unsigned num_banks,
- const core_config *config, opndcoll_rfu_t *rfu, bool sub_core_model,
- unsigned reg_id, unsigned banks_per_sched) {
+void opndcoll_rfu_t::collector_unit_t::init(unsigned n, unsigned num_banks,
+ const core_config *config,
+ opndcoll_rfu_t *rfu,
+ bool sub_core_model,
+ unsigned reg_id,
+ unsigned banks_per_sched) {
m_rfu = rfu;
m_cuid = n;
m_num_banks = num_banks;
@@ -4376,7 +4398,7 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set,
warp_inst_t **pipeline_reg = pipeline_reg_set->get_ready();
if ((pipeline_reg) and !((*pipeline_reg)->empty())) {
m_warp_id = (*pipeline_reg)->warp_id();
- std::vector<int> prev_regs; // remove duplicate regs within same instr
+ std::vector<int> prev_regs; // remove duplicate regs within same instr
for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
int reg_num =
(*pipeline_reg)
@@ -4384,14 +4406,13 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set,
// function_info::ptx_decode_inst
bool new_reg = true;
for (auto r : prev_regs) {
- if (r == reg_num)
- new_reg = false;
+ if (r == reg_num) new_reg = false;
}
- if (reg_num >= 0 && new_reg) { // valid register
+ if (reg_num >= 0 && new_reg) { // valid register
prev_regs.push_back(reg_num);
- m_src_op[op] = op_t(this, op, reg_num, m_num_banks,
- m_sub_core_model, m_num_banks_per_sched,
- (*pipeline_reg)->get_schd_id());
+ m_src_op[op] =
+ op_t(this, op, reg_num, m_num_banks, m_sub_core_model,
+ m_num_banks_per_sched, (*pipeline_reg)->get_schd_id());
m_not_ready.set(op);
} else
m_src_op[op] = op_t();
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 22:29:37 +0000