diff options
Diffstat (limited to 'src')
29 files changed, 2582 insertions, 2227 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index ed7347d..fd056c6 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Timothy Rogers, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Timothy Rogers, +// Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, Timothy G. +// Rogers The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -28,7 +29,6 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. - #include "abstract_hardware_model.h" #include <sys/stat.h> #include <algorithm> @@ -284,7 +284,7 @@ void warp_inst_t::broadcast_barrier_reduction( void warp_inst_t::generate_mem_accesses() { if (empty() || op == MEMORY_BARRIER_OP || m_mem_accesses_created) return; if (!((op == LOAD_OP) || (op == TENSOR_CORE_LOAD_OP) || (op == STORE_OP) || - (op == TENSOR_CORE_STORE_OP) )) + (op == TENSOR_CORE_STORE_OP))) return; if (m_warp_active_mask.count() == 0) return; // predicated off @@ -292,8 +292,8 @@ void warp_inst_t::generate_mem_accesses() { assert(is_load() || is_store()); - //if((space.get_type() != tex_space) && (space.get_type() != const_space)) - assert(m_per_scalar_thread_valid); // need address information per thread + // if((space.get_type() != tex_space) && (space.get_type() != const_space)) + assert(m_per_scalar_thread_valid); // need address information per thread bool is_write = is_store(); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ebf6535..e5f3b78 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University +// Copyright (c) 2009-2021, Tor M. Aamodt, Inderpreet Singh, Vijay Kandiah, +// Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, Timothy G. Rogers The +// University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -64,24 +65,24 @@ enum _memory_space_t { #ifndef COEFF_STRUCT #define COEFF_STRUCT -struct PowerscalingCoefficients{ - double int_coeff; - double int_mul_coeff; - double int_mul24_coeff; - double int_mul32_coeff; - double int_div_coeff; - double fp_coeff; - double dp_coeff; - double fp_mul_coeff; - double fp_div_coeff; - double dp_mul_coeff; - double dp_div_coeff; - double sqrt_coeff; - double log_coeff; - double sin_coeff; - double exp_coeff; - double tensor_coeff; - double tex_coeff; +struct PowerscalingCoefficients { + double int_coeff; + double int_mul_coeff; + double int_mul24_coeff; + double int_mul32_coeff; + double int_div_coeff; + double fp_coeff; + double dp_coeff; + double fp_mul_coeff; + double fp_div_coeff; + double dp_mul_coeff; + double dp_div_coeff; + double sqrt_coeff; + double log_coeff; + double sin_coeff; + double exp_coeff; + double tensor_coeff; + double tex_coeff; }; #endif @@ -974,18 +975,22 @@ class inst_t { memory_op == memory_store); } - bool is_fp() const { return ((sp_op == FP__OP));} //VIJAY - bool is_fpdiv() const { return ((sp_op == FP_DIV_OP));} - bool is_fpmul() const { return ((sp_op == FP_MUL_OP));} - bool is_dp() const { return ((sp_op == DP___OP));} - bool is_dpdiv() const { return ((sp_op == DP_DIV_OP));} - bool is_dpmul() const { return ((sp_op == DP_MUL_OP));} - bool is_imul() const { return ((sp_op == INT_MUL_OP));} - bool is_imul24() const { return ((sp_op == INT_MUL24_OP));} - bool is_imul32() const { return ((sp_op == INT_MUL32_OP));} - bool is_idiv() const { return ((sp_op == INT_DIV_OP));} - bool is_sfu() const {return ((sp_op == FP_SQRT_OP) || (sp_op == FP_LG_OP) || (sp_op == FP_SIN_OP) || (sp_op == FP_EXP_OP) || (sp_op == TENSOR__OP));} - bool is_alu() const {return (sp_op == INT__OP);} + bool is_fp() const { return ((sp_op == FP__OP)); } // VIJAY + bool is_fpdiv() const { return ((sp_op == FP_DIV_OP)); } + bool is_fpmul() const { return ((sp_op == FP_MUL_OP)); } + bool is_dp() const { return ((sp_op == DP___OP)); } + bool is_dpdiv() const { return ((sp_op == DP_DIV_OP)); } + bool is_dpmul() const { return ((sp_op == DP_MUL_OP)); } + bool is_imul() const { return ((sp_op == INT_MUL_OP)); } + bool is_imul24() const { return ((sp_op == INT_MUL24_OP)); } + bool is_imul32() const { return ((sp_op == INT_MUL32_OP)); } + bool is_idiv() const { return ((sp_op == INT_DIV_OP)); } + bool is_sfu() const { + return ((sp_op == FP_SQRT_OP) || (sp_op == FP_LG_OP) || + (sp_op == FP_SIN_OP) || (sp_op == FP_EXP_OP) || + (sp_op == TENSOR__OP)); + } + bool is_alu() const { return (sp_op == INT__OP); } unsigned get_num_operands() const { return num_operands; } unsigned get_num_regs() const { return num_regs; } @@ -1010,7 +1015,7 @@ class inst_t { operation_pipeline op_pipe; // code (uarch visible) identify the pipeline of // the operation (SP, SFU or MEM) mem_operation mem_op; // code (uarch visible) identify memory type - bool const_cache_operand; // has a load from constant memory as an operand + bool const_cache_operand; // has a load from constant memory as an operand _memory_op_t memory_op; // memory_op used by ptxplus unsigned num_operands; unsigned num_regs; // count vector operand as one register operand @@ -1057,7 +1062,7 @@ class warp_inst_t : public inst_t { m_empty = true; m_config = NULL; - // Ni: + // Ni: m_is_ldgsts = false; m_is_ldgdepbar = false; m_is_depbar = false; @@ -1077,7 +1082,7 @@ class warp_inst_t : public inst_t { m_is_cdp = 0; should_do_atomic = true; - // Ni: + // Ni: m_is_ldgsts = false; m_is_ldgdepbar = false; m_is_depbar = false; diff --git a/src/accelwattch/XML_Parse.cc b/src/accelwattch/XML_Parse.cc index eaec748..801de6f 100644 --- a/src/accelwattch/XML_Parse.cc +++ b/src/accelwattch/XML_Parse.cc @@ -30,14 +30,13 @@ ***************************************************************************/
/********************************************************************
* Modified by:
- * Jingwen Leng, University of Texas, Austin
- * Syed Gilani, University of Wisconsin–Madison
+ * Jingwen Leng, University of Texas, Austin
+ * Syed Gilani, University of Wisconsin–Madison
* Tayler Hetherington, University of British Columbia
* Ahmed ElTantawy, University of British Columbia
* Vijay Kandiah, Northwestern University
********************************************************************/
-
#include "XML_Parse.h"
#include <stdio.h>
#include <string>
@@ -45,14 +44,18 @@ using namespace std;
-const char * perf_count_label[] = {
- "TOT_INST,", "FP_INT,", "IC_H,", "IC_M,", "DC_RH,", "DC_RM,", "DC_WH,", "DC_WM,",
- "TC_H,", "TC_M,", "CC_H,", "CC_M,", "SHRD_ACC,", "REG_RD,", "REG_WR,", "NON_REG_OPs,",
- "INT_ACC,", "FPU_ACC,", "DPU_ACC,", "INT_MUL24_ACC,", "INT_MUL32_ACC,", "INT_MUL_ACC,","INT_DIV_ACC,",
- "FP_MUL_ACC,", "FP_DIV_ACC,", "FP_SQRT_ACC,", "FP_LG_ACC,", "FP_SIN_ACC,", "FP_EXP_ACC,", "DP_MUL_ACC,",
- "DP_DIV_ACC,", "TENSOR_ACC,", "TEX_ACC,", "MEM_RD,","MEM_WR,", "MEM_PRE,", "L2_RH,", "L2_RM,", "L2_WH,",
- "L2_WM,", "NOC_A,", "PIPE_A,", "IDLE_CORE_N,", "constant_power"};
-
+const char* perf_count_label[] = {
+ "TOT_INST,", "FP_INT,", "IC_H,", "IC_M,",
+ "DC_RH,", "DC_RM,", "DC_WH,", "DC_WM,",
+ "TC_H,", "TC_M,", "CC_H,", "CC_M,",
+ "SHRD_ACC,", "REG_RD,", "REG_WR,", "NON_REG_OPs,",
+ "INT_ACC,", "FPU_ACC,", "DPU_ACC,", "INT_MUL24_ACC,",
+ "INT_MUL32_ACC,", "INT_MUL_ACC,", "INT_DIV_ACC,", "FP_MUL_ACC,",
+ "FP_DIV_ACC,", "FP_SQRT_ACC,", "FP_LG_ACC,", "FP_SIN_ACC,",
+ "FP_EXP_ACC,", "DP_MUL_ACC,", "DP_DIV_ACC,", "TENSOR_ACC,",
+ "TEX_ACC,", "MEM_RD,", "MEM_WR,", "MEM_PRE,",
+ "L2_RH,", "L2_RM,", "L2_WH,", "L2_WM,",
+ "NOC_A,", "PIPE_A,", "IDLE_CORE_N,", "constant_power"};
void ParseXML::parse(char* filepath) {
unsigned int i, j, k, m, n;
@@ -171,8 +174,6 @@ void ParseXML::parse(char* filepath) { continue;
}
-
-
if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
"static_cat1_flane") == 0) {
sys.static_cat1_flane =
@@ -355,7 +356,6 @@ void ParseXML::parse(char* filepath) { continue;
}
-
if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
"target_chip_area") == 0) {
sys.target_chip_area =
@@ -615,106 +615,106 @@ void ParseXML::parse(char* filepath) { atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "INT_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "INT_ACC") == 0) {
sys.scaling_coefficients[INT_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_ACC") == 0) {
sys.scaling_coefficients[FP_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "DP_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "DP_ACC") == 0) {
sys.scaling_coefficients[DP_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "INT_MUL24_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "INT_MUL24_ACC") == 0) {
sys.scaling_coefficients[INT_MUL24_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "INT_MUL32_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "INT_MUL32_ACC") == 0) {
sys.scaling_coefficients[INT_MUL32_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "INT_MUL_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "INT_MUL_ACC") == 0) {
sys.scaling_coefficients[INT_MUL_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "INT_DIV_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "INT_DIV_ACC") == 0) {
sys.scaling_coefficients[INT_DIV_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_MUL_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_MUL_ACC") == 0) {
sys.scaling_coefficients[FP_MUL_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_DIV_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_DIV_ACC") == 0) {
sys.scaling_coefficients[FP_DIV_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_SQRT_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_SQRT_ACC") == 0) {
sys.scaling_coefficients[FP_SQRT_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_LG_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_LG_ACC") == 0) {
sys.scaling_coefficients[FP_LG_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_SIN_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_SIN_ACC") == 0) {
sys.scaling_coefficients[FP_SIN_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "FP_EXP_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "FP_EXP_ACC") == 0) {
sys.scaling_coefficients[FP_EXP_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "DP_MUL_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "DP_MUL_ACC") == 0) {
sys.scaling_coefficients[DP_MUL_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "DP_DIV_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "DP_DIV_ACC") == 0) {
sys.scaling_coefficients[DP_DIV_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "TENSOR_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "TENSOR_ACC") == 0) {
sys.scaling_coefficients[TENSOR_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
- if (strcmp(xNode2.getChildNode("param",i).getAttribute("name"),
- "TEX_ACC")==0) {
+ if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
+ "TEX_ACC") == 0) {
sys.scaling_coefficients[TEX_ACC] =
- atof(xNode2.getChildNode("param",i).getAttribute("value"));
+ atof(xNode2.getChildNode("param", i).getAttribute("value"));
continue;
}
if (strcmp(xNode2.getChildNode("param", i).getAttribute("name"),
diff --git a/src/accelwattch/XML_Parse.h b/src/accelwattch/XML_Parse.h index c82359f..176b82f 100644 --- a/src/accelwattch/XML_Parse.h +++ b/src/accelwattch/XML_Parse.h @@ -30,8 +30,8 @@ ***************************************************************************/
/********************************************************************
* Modified by:
- * Jingwen Leng, University of Texas, Austin
- * Syed Gilani, University of Wisconsin–Madison
+ * Jingwen Leng, University of Texas, Austin
+ * Syed Gilani, University of Wisconsin–Madison
* Tayler Hetherington, University of British Columbia
* Ahmed ElTantawy, University of British Columbia
* Vijay Kandiah, Northwestern University
@@ -70,7 +70,7 @@ ToXMLStringTool tx,tx2; extern const char* perf_count_label[];
enum perf_count_t {
- TOT_INST=0,
+ TOT_INST = 0,
FP_INT,
IC_H,
IC_M,
@@ -86,23 +86,23 @@ enum perf_count_t { REG_RD,
REG_WR,
NON_REG_OPs,
- INT_ACC, //SPU
- FP_ACC, //FPU
- DP_ACC, //FPU
- INT_MUL24_ACC, //SFU
- INT_MUL32_ACC, //SFU
- INT_MUL_ACC, //SFU
- INT_DIV_ACC, //SFU
- FP_MUL_ACC, //SFU
- FP_DIV_ACC, //SFU
- FP_SQRT_ACC, //SFU
- FP_LG_ACC, //SFU
- FP_SIN_ACC, //SFU
- FP_EXP_ACC, //SFU
- DP_MUL_ACC, //SFU
- DP_DIV_ACC, //SFU
- TENSOR_ACC, //SFU
- TEX_ACC, //SFU
+ INT_ACC, // SPU
+ FP_ACC, // FPU
+ DP_ACC, // FPU
+ INT_MUL24_ACC, // SFU
+ INT_MUL32_ACC, // SFU
+ INT_MUL_ACC, // SFU
+ INT_DIV_ACC, // SFU
+ FP_MUL_ACC, // SFU
+ FP_DIV_ACC, // SFU
+ FP_SQRT_ACC, // SFU
+ FP_LG_ACC, // SFU
+ FP_SIN_ACC, // SFU
+ FP_EXP_ACC, // SFU
+ DP_MUL_ACC, // SFU
+ DP_DIV_ACC, // SFU
+ TENSOR_ACC, // SFU
+ TEX_ACC, // SFU
MEM_RD,
MEM_WR,
MEM_PRE,
diff --git a/src/accelwattch/gpgpu_sim_wrapper.cc b/src/accelwattch/gpgpu_sim_wrapper.cc index 67d9daa..4883c7c 100644 --- a/src/accelwattch/gpgpu_sim_wrapper.cc +++ b/src/accelwattch/gpgpu_sim_wrapper.cc @@ -1,16 +1,17 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Ahmed ElTantawy, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Ahmed ElTantawy, +// Vijay Kandiah, Nikos Hardavellas The University of British Columbia, +// Northwestern University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -33,14 +34,16 @@ #define SFU_BASE_POWER 0 static const char* pwr_cmp_label[] = { - "IBP,", "ICP,", "DCP,", "TCP,", "CCP,", "SHRDP,", "RFP,", "INTP,", - "FPUP,", "DPUP,", "INT_MUL24P,", "INT_MUL32P,", "INT_MULP,", "INT_DIVP,", - "FP_MULP,", "FP_DIVP,", "FP_SQRTP,", "FP_LGP,", "FP_SINP,", "FP_EXP,", - "DP_MULP,", "DP_DIVP,", "TENSORP,", "TEXP,", "SCHEDP,", "L2CP,", "MCP,", "NOCP,", - "DRAMP,", "PIPEP,", "IDLE_COREP,", "CONSTP", "STATICP"}; + "IBP,", "ICP,", "DCP,", "TCP,", "CCP,", + "SHRDP,", "RFP,", "INTP,", "FPUP,", "DPUP,", + "INT_MUL24P,", "INT_MUL32P,", "INT_MULP,", "INT_DIVP,", "FP_MULP,", + "FP_DIVP,", "FP_SQRTP,", "FP_LGP,", "FP_SINP,", "FP_EXP,", + "DP_MULP,", "DP_DIVP,", "TENSORP,", "TEXP,", "SCHEDP,", + "L2CP,", "MCP,", "NOCP,", "DRAMP,", "PIPEP,", + "IDLE_COREP,", "CONSTP", "STATICP"}; enum pwr_cmp_t { - IBP=0, + IBP = 0, ICP, DCP, TCP, @@ -77,7 +80,8 @@ enum pwr_cmp_t { }; gpgpu_sim_wrapper::gpgpu_sim_wrapper(bool power_simulation_enabled, - char* xmlfile, int power_simulation_mode, bool dvfs_enabled) { + char* xmlfile, int power_simulation_mode, + bool dvfs_enabled) { kernel_sample_count = 0; total_sample_count = 0; @@ -142,7 +146,8 @@ bool gpgpu_sim_wrapper::sanity_check(double a, double b) { return false; } void gpgpu_sim_wrapper::init_mcpat_hw_mode(unsigned gpu_sim_cycle) { - p->sys.total_cycles = gpu_sim_cycle; //total simulated cycles for current kernel + p->sys.total_cycles = + gpu_sim_cycle; // total simulated cycles for current kernel } void gpgpu_sim_wrapper::init_mcpat( @@ -150,9 +155,9 @@ void gpgpu_sim_wrapper::init_mcpat( char* metric_trace_filename, char* steady_state_filename, bool power_sim_enabled, bool trace_enabled, bool steady_state_enabled, bool power_per_cycle_dump, double steady_power_deviation, - double steady_min_period, int zlevel, double init_val, - int stat_sample_freq, int power_sim_mode, bool dvfs_enabled, - unsigned clock_freq, unsigned num_shaders) { + double steady_min_period, int zlevel, double init_val, int stat_sample_freq, + int power_sim_mode, bool dvfs_enabled, unsigned clock_freq, + unsigned num_shaders) { // Write File Headers for (-metrics trace, -power trace) reset_counters(); @@ -382,10 +387,7 @@ void gpgpu_sim_wrapper::set_l2cache_power(double read_hits, double read_misses, sample_perf_counters[L2_WM] = write_misses; } -void gpgpu_sim_wrapper::set_num_cores(double num_core) { - - num_cores = num_core; -} +void gpgpu_sim_wrapper::set_num_cores(double num_core) { num_cores = num_core; } void gpgpu_sim_wrapper::set_idle_core_power(double num_idle_core) { p->sys.num_idle_cores = num_idle_core; @@ -411,29 +413,25 @@ void gpgpu_sim_wrapper::set_mem_ctrl_power(double reads, double writes, sample_perf_counters[MEM_PRE] = dram_precharge; } - void gpgpu_sim_wrapper::set_model_voltage(double model_voltage) { - modeled_chip_voltage = model_voltage; + modeled_chip_voltage = model_voltage; } - void gpgpu_sim_wrapper::set_exec_unit_power(double fpu_accesses, double ialu_accesses, double sfu_accesses) { p->sys.core[0].fpu_accesses = fpu_accesses; tot_fpu_accesses = fpu_accesses; - //Integer ALU (not present in Tesla) + // Integer ALU (not present in Tesla) p->sys.core[0].ialu_accesses = ialu_accesses; - //Sfu accesses + // Sfu accesses p->sys.core[0].mul_accesses = sfu_accesses; tot_sfu_accesses = sfu_accesses; } -PowerscalingCoefficients * gpgpu_sim_wrapper::get_scaling_coeffs() -{ - - PowerscalingCoefficients * scalingCoeffs = new PowerscalingCoefficients(); +PowerscalingCoefficients* gpgpu_sim_wrapper::get_scaling_coeffs() { + PowerscalingCoefficients* scalingCoeffs = new PowerscalingCoefficients(); scalingCoeffs->int_coeff = p->sys.scaling_coefficients[INT_ACC]; scalingCoeffs->int_mul_coeff = p->sys.scaling_coefficients[INT_MUL_ACC]; @@ -453,68 +451,55 @@ PowerscalingCoefficients * gpgpu_sim_wrapper::get_scaling_coeffs() scalingCoeffs->tensor_coeff = p->sys.scaling_coefficients[TENSOR_ACC]; scalingCoeffs->tex_coeff = p->sys.scaling_coefficients[TEX_ACC]; return scalingCoeffs; - } -void gpgpu_sim_wrapper::set_int_accesses(double ialu_accesses, - double imul24_accesses, - double imul32_accesses, - double imul_accesses, - double idiv_accesses) -{ - - sample_perf_counters[INT_ACC]=ialu_accesses; - sample_perf_counters[INT_MUL24_ACC]=imul24_accesses; - sample_perf_counters[INT_MUL32_ACC]=imul32_accesses; - sample_perf_counters[INT_MUL_ACC]=imul_accesses; - sample_perf_counters[INT_DIV_ACC]=idiv_accesses; +void gpgpu_sim_wrapper::set_int_accesses(double ialu_accesses, + double imul24_accesses, + double imul32_accesses, + double imul_accesses, + double idiv_accesses) { + sample_perf_counters[INT_ACC] = ialu_accesses; + sample_perf_counters[INT_MUL24_ACC] = imul24_accesses; + sample_perf_counters[INT_MUL32_ACC] = imul32_accesses; + sample_perf_counters[INT_MUL_ACC] = imul_accesses; + sample_perf_counters[INT_DIV_ACC] = idiv_accesses; } -void gpgpu_sim_wrapper::set_dp_accesses(double dpu_accesses, - double dpmul_accesses, - double dpdiv_accesses) -{ - sample_perf_counters[DP_ACC]=dpu_accesses; - sample_perf_counters[DP_MUL_ACC]=dpmul_accesses; - sample_perf_counters[DP_DIV_ACC]=dpdiv_accesses; +void gpgpu_sim_wrapper::set_dp_accesses(double dpu_accesses, + double dpmul_accesses, + double dpdiv_accesses) { + sample_perf_counters[DP_ACC] = dpu_accesses; + sample_perf_counters[DP_MUL_ACC] = dpmul_accesses; + sample_perf_counters[DP_DIV_ACC] = dpdiv_accesses; } -void gpgpu_sim_wrapper::set_fp_accesses(double fpu_accesses, - double fpmul_accesses, - double fpdiv_accesses) -{ - sample_perf_counters[FP_ACC]=fpu_accesses; - sample_perf_counters[FP_MUL_ACC]=fpmul_accesses; - sample_perf_counters[FP_DIV_ACC]=fpdiv_accesses; +void gpgpu_sim_wrapper::set_fp_accesses(double fpu_accesses, + double fpmul_accesses, + double fpdiv_accesses) { + sample_perf_counters[FP_ACC] = fpu_accesses; + sample_perf_counters[FP_MUL_ACC] = fpmul_accesses; + sample_perf_counters[FP_DIV_ACC] = fpdiv_accesses; } -void gpgpu_sim_wrapper::set_trans_accesses(double sqrt_accesses, - double log_accesses, - double sin_accesses, - double exp_accesses) -{ - - sample_perf_counters[FP_SQRT_ACC]=sqrt_accesses; - sample_perf_counters[FP_LG_ACC]=log_accesses; - sample_perf_counters[FP_SIN_ACC]=sin_accesses; - sample_perf_counters[FP_EXP_ACC]=exp_accesses; - +void gpgpu_sim_wrapper::set_trans_accesses(double sqrt_accesses, + double log_accesses, + double sin_accesses, + double exp_accesses) { + sample_perf_counters[FP_SQRT_ACC] = sqrt_accesses; + sample_perf_counters[FP_LG_ACC] = log_accesses; + sample_perf_counters[FP_SIN_ACC] = sin_accesses; + sample_perf_counters[FP_EXP_ACC] = exp_accesses; } -void gpgpu_sim_wrapper::set_tensor_accesses(double tensor_accesses) -{ - sample_perf_counters[TENSOR_ACC]=tensor_accesses; - +void gpgpu_sim_wrapper::set_tensor_accesses(double tensor_accesses) { + sample_perf_counters[TENSOR_ACC] = tensor_accesses; } -void gpgpu_sim_wrapper::set_tex_accesses(double tex_accesses) -{ - sample_perf_counters[TEX_ACC]=tex_accesses; - +void gpgpu_sim_wrapper::set_tex_accesses(double tex_accesses) { + sample_perf_counters[TEX_ACC] = tex_accesses; } -void gpgpu_sim_wrapper::set_avg_active_threads(float active_threads) -{ +void gpgpu_sim_wrapper::set_avg_active_threads(float active_threads) { avg_threads_per_warp = (unsigned)ceil(active_threads); avg_threads_per_warp_tot += active_threads; } @@ -536,7 +521,8 @@ void gpgpu_sim_wrapper::power_metrics_calculations() { kernel_sample_count++; // Current sample power - double sample_power = proc->rt_power.readOp.dynamic + sample_cmp_pwr[CONSTP] + sample_cmp_pwr[STATICP]; + double sample_power = proc->rt_power.readOp.dynamic + sample_cmp_pwr[CONSTP] + + sample_cmp_pwr[STATICP]; // double sample_power; // for(unsigned i=0; i<num_pwr_cmps; i++){ // sample_power+=sample_cmp_pwr[i]; //fix for dvfs @@ -602,371 +588,503 @@ void gpgpu_sim_wrapper::print_trace_files() { close_files(); } -void gpgpu_sim_wrapper::update_coefficients() -{ +void gpgpu_sim_wrapper::update_coefficients() { + initpower_coeff[FP_INT] = proc->cores[0]->get_coefficient_fpint_insts(); + effpower_coeff[FP_INT] = + initpower_coeff[FP_INT] * p->sys.scaling_coefficients[FP_INT]; - initpower_coeff[FP_INT]=proc->cores[0]->get_coefficient_fpint_insts(); - effpower_coeff[FP_INT]=initpower_coeff[FP_INT] * p->sys.scaling_coefficients[FP_INT]; + initpower_coeff[TOT_INST] = proc->cores[0]->get_coefficient_tot_insts(); + effpower_coeff[TOT_INST] = + initpower_coeff[TOT_INST] * p->sys.scaling_coefficients[TOT_INST]; - initpower_coeff[TOT_INST]=proc->cores[0]->get_coefficient_tot_insts(); - effpower_coeff[TOT_INST]=initpower_coeff[TOT_INST] * p->sys.scaling_coefficients[TOT_INST]; + initpower_coeff[REG_RD] = + proc->cores[0]->get_coefficient_regreads_accesses() * + (proc->cores[0]->exu->rf_fu_clockRate / proc->cores[0]->exu->clockRate); + initpower_coeff[REG_WR] = + proc->cores[0]->get_coefficient_regwrites_accesses() * + (proc->cores[0]->exu->rf_fu_clockRate / proc->cores[0]->exu->clockRate); + initpower_coeff[NON_REG_OPs] = + proc->cores[0]->get_coefficient_noregfileops_accesses() * + (proc->cores[0]->exu->rf_fu_clockRate / proc->cores[0]->exu->clockRate); + effpower_coeff[REG_RD] = + initpower_coeff[REG_RD] * p->sys.scaling_coefficients[REG_RD]; + effpower_coeff[REG_WR] = + initpower_coeff[REG_WR] * p->sys.scaling_coefficients[REG_WR]; + effpower_coeff[NON_REG_OPs] = + initpower_coeff[NON_REG_OPs] * p->sys.scaling_coefficients[NON_REG_OPs]; - initpower_coeff[REG_RD]=proc->cores[0]->get_coefficient_regreads_accesses()*(proc->cores[0]->exu->rf_fu_clockRate/proc->cores[0]->exu->clockRate); - initpower_coeff[REG_WR]=proc->cores[0]->get_coefficient_regwrites_accesses()*(proc->cores[0]->exu->rf_fu_clockRate/proc->cores[0]->exu->clockRate); - initpower_coeff[NON_REG_OPs]=proc->cores[0]->get_coefficient_noregfileops_accesses()*(proc->cores[0]->exu->rf_fu_clockRate/proc->cores[0]->exu->clockRate); - effpower_coeff[REG_RD]=initpower_coeff[REG_RD]*p->sys.scaling_coefficients[REG_RD]; - effpower_coeff[REG_WR]=initpower_coeff[REG_WR]*p->sys.scaling_coefficients[REG_WR]; - effpower_coeff[NON_REG_OPs]=initpower_coeff[NON_REG_OPs]*p->sys.scaling_coefficients[NON_REG_OPs]; + initpower_coeff[IC_H] = proc->cores[0]->get_coefficient_icache_hits(); + initpower_coeff[IC_M] = proc->cores[0]->get_coefficient_icache_misses(); + effpower_coeff[IC_H] = + initpower_coeff[IC_H] * p->sys.scaling_coefficients[IC_H]; + effpower_coeff[IC_M] = + initpower_coeff[IC_M] * p->sys.scaling_coefficients[IC_M]; - initpower_coeff[IC_H]=proc->cores[0]->get_coefficient_icache_hits(); - initpower_coeff[IC_M]=proc->cores[0]->get_coefficient_icache_misses(); - effpower_coeff[IC_H]=initpower_coeff[IC_H]*p->sys.scaling_coefficients[IC_H]; - effpower_coeff[IC_M]=initpower_coeff[IC_M]*p->sys.scaling_coefficients[IC_M]; + initpower_coeff[CC_H] = (proc->cores[0]->get_coefficient_ccache_readhits() + + proc->get_coefficient_readcoalescing()); + initpower_coeff[CC_M] = (proc->cores[0]->get_coefficient_ccache_readmisses() + + proc->get_coefficient_readcoalescing()); + effpower_coeff[CC_H] = + initpower_coeff[CC_H] * p->sys.scaling_coefficients[CC_H]; + effpower_coeff[CC_M] = + initpower_coeff[CC_M] * p->sys.scaling_coefficients[CC_M]; - initpower_coeff[CC_H]=(proc->cores[0]->get_coefficient_ccache_readhits()+proc->get_coefficient_readcoalescing()); - initpower_coeff[CC_M]=(proc->cores[0]->get_coefficient_ccache_readmisses()+proc->get_coefficient_readcoalescing()); - effpower_coeff[CC_H]=initpower_coeff[CC_H]*p->sys.scaling_coefficients[CC_H]; - effpower_coeff[CC_M]=initpower_coeff[CC_M]*p->sys.scaling_coefficients[CC_M]; + initpower_coeff[TC_H] = (proc->cores[0]->get_coefficient_tcache_readhits() + + proc->get_coefficient_readcoalescing()); + initpower_coeff[TC_M] = (proc->cores[0]->get_coefficient_tcache_readmisses() + + proc->get_coefficient_readcoalescing()); + effpower_coeff[TC_H] = + initpower_coeff[TC_H] * p->sys.scaling_coefficients[TC_H]; + effpower_coeff[TC_M] = + initpower_coeff[TC_M] * p->sys.scaling_coefficients[TC_M]; - initpower_coeff[TC_H]=(proc->cores[0]->get_coefficient_tcache_readhits()+proc->get_coefficient_readcoalescing()); - initpower_coeff[TC_M]=(proc->cores[0]->get_coefficient_tcache_readmisses()+proc->get_coefficient_readcoalescing()); - effpower_coeff[TC_H]=initpower_coeff[TC_H]*p->sys.scaling_coefficients[TC_H]; - effpower_coeff[TC_M]=initpower_coeff[TC_M]*p->sys.scaling_coefficients[TC_M]; + initpower_coeff[SHRD_ACC] = + proc->cores[0]->get_coefficient_sharedmemory_readhits(); + effpower_coeff[SHRD_ACC] = + initpower_coeff[SHRD_ACC] * p->sys.scaling_coefficients[SHRD_ACC]; - initpower_coeff[SHRD_ACC]=proc->cores[0]->get_coefficient_sharedmemory_readhits(); - effpower_coeff[SHRD_ACC]=initpower_coeff[SHRD_ACC]*p->sys.scaling_coefficients[SHRD_ACC]; + initpower_coeff[DC_RH] = (proc->cores[0]->get_coefficient_dcache_readhits() + + proc->get_coefficient_readcoalescing()); + initpower_coeff[DC_RM] = + (proc->cores[0]->get_coefficient_dcache_readmisses() + + proc->get_coefficient_readcoalescing()); + initpower_coeff[DC_WH] = (proc->cores[0]->get_coefficient_dcache_writehits() + + proc->get_coefficient_writecoalescing()); + initpower_coeff[DC_WM] = + (proc->cores[0]->get_coefficient_dcache_writemisses() + + proc->get_coefficient_writecoalescing()); + effpower_coeff[DC_RH] = + initpower_coeff[DC_RH] * p->sys.scaling_coefficients[DC_RH]; + effpower_coeff[DC_RM] = + initpower_coeff[DC_RM] * p->sys.scaling_coefficients[DC_RM]; + effpower_coeff[DC_WH] = + initpower_coeff[DC_WH] * p->sys.scaling_coefficients[DC_WH]; + effpower_coeff[DC_WM] = + initpower_coeff[DC_WM] * p->sys.scaling_coefficients[DC_WM]; - initpower_coeff[DC_RH]=(proc->cores[0]->get_coefficient_dcache_readhits() + proc->get_coefficient_readcoalescing()); - initpower_coeff[DC_RM]=(proc->cores[0]->get_coefficient_dcache_readmisses() + proc->get_coefficient_readcoalescing()); - initpower_coeff[DC_WH]=(proc->cores[0]->get_coefficient_dcache_writehits() + proc->get_coefficient_writecoalescing()); - initpower_coeff[DC_WM]=(proc->cores[0]->get_coefficient_dcache_writemisses() + proc->get_coefficient_writecoalescing()); - effpower_coeff[DC_RH]=initpower_coeff[DC_RH]*p->sys.scaling_coefficients[DC_RH]; - effpower_coeff[DC_RM]=initpower_coeff[DC_RM]*p->sys.scaling_coefficients[DC_RM]; - effpower_coeff[DC_WH]=initpower_coeff[DC_WH]*p->sys.scaling_coefficients[DC_WH]; - effpower_coeff[DC_WM]=initpower_coeff[DC_WM]*p->sys.scaling_coefficients[DC_WM]; + initpower_coeff[L2_RH] = proc->get_coefficient_l2_read_hits(); + initpower_coeff[L2_RM] = proc->get_coefficient_l2_read_misses(); + initpower_coeff[L2_WH] = proc->get_coefficient_l2_write_hits(); + initpower_coeff[L2_WM] = proc->get_coefficient_l2_write_misses(); + effpower_coeff[L2_RH] = + initpower_coeff[L2_RH] * p->sys.scaling_coefficients[L2_RH]; + effpower_coeff[L2_RM] = + initpower_coeff[L2_RM] * p->sys.scaling_coefficients[L2_RM]; + effpower_coeff[L2_WH] = + initpower_coeff[L2_WH] * p->sys.scaling_coefficients[L2_WH]; + effpower_coeff[L2_WM] = + initpower_coeff[L2_WM] * p->sys.scaling_coefficients[L2_WM]; - initpower_coeff[L2_RH]=proc->get_coefficient_l2_read_hits(); - initpower_coeff[L2_RM]=proc->get_coefficient_l2_read_misses(); - initpower_coeff[L2_WH]=proc->get_coefficient_l2_write_hits(); - initpower_coeff[L2_WM]=proc->get_coefficient_l2_write_misses(); - effpower_coeff[L2_RH]=initpower_coeff[L2_RH]*p->sys.scaling_coefficients[L2_RH]; - effpower_coeff[L2_RM]=initpower_coeff[L2_RM]*p->sys.scaling_coefficients[L2_RM]; - effpower_coeff[L2_WH]=initpower_coeff[L2_WH]*p->sys.scaling_coefficients[L2_WH]; - effpower_coeff[L2_WM]=initpower_coeff[L2_WM]*p->sys.scaling_coefficients[L2_WM]; + initpower_coeff[IDLE_CORE_N] = + p->sys.idle_core_power * proc->cores[0]->executionTime; + effpower_coeff[IDLE_CORE_N] = + initpower_coeff[IDLE_CORE_N] * p->sys.scaling_coefficients[IDLE_CORE_N]; - initpower_coeff[IDLE_CORE_N]=p->sys.idle_core_power * proc->cores[0]->executionTime; - effpower_coeff[IDLE_CORE_N]=initpower_coeff[IDLE_CORE_N]*p->sys.scaling_coefficients[IDLE_CORE_N]; + initpower_coeff[PIPE_A] = proc->cores[0]->get_coefficient_duty_cycle(); + effpower_coeff[PIPE_A] = + initpower_coeff[PIPE_A] * p->sys.scaling_coefficients[PIPE_A]; - initpower_coeff[PIPE_A]=proc->cores[0]->get_coefficient_duty_cycle(); - effpower_coeff[PIPE_A]=initpower_coeff[PIPE_A]*p->sys.scaling_coefficients[PIPE_A]; + initpower_coeff[MEM_RD] = proc->get_coefficient_mem_reads(); + initpower_coeff[MEM_WR] = proc->get_coefficient_mem_writes(); + initpower_coeff[MEM_PRE] = proc->get_coefficient_mem_pre(); + effpower_coeff[MEM_RD] = + initpower_coeff[MEM_RD] * p->sys.scaling_coefficients[MEM_RD]; + effpower_coeff[MEM_WR] = + initpower_coeff[MEM_WR] * p->sys.scaling_coefficients[MEM_WR]; + effpower_coeff[MEM_PRE] = + initpower_coeff[MEM_PRE] * p->sys.scaling_coefficients[MEM_PRE]; - initpower_coeff[MEM_RD]=proc->get_coefficient_mem_reads(); - initpower_coeff[MEM_WR]=proc->get_coefficient_mem_writes(); - initpower_coeff[MEM_PRE]=proc->get_coefficient_mem_pre(); - effpower_coeff[MEM_RD]=initpower_coeff[MEM_RD]*p->sys.scaling_coefficients[MEM_RD]; - effpower_coeff[MEM_WR]=initpower_coeff[MEM_WR]*p->sys.scaling_coefficients[MEM_WR]; - effpower_coeff[MEM_PRE]=initpower_coeff[MEM_PRE]*p->sys.scaling_coefficients[MEM_PRE]; - double fp_coeff = proc->cores[0]->get_coefficient_fpu_accesses(); double sfu_coeff = proc->cores[0]->get_coefficient_sfu_accesses(); - initpower_coeff[INT_ACC]= proc->cores[0]->get_coefficient_ialu_accesses()*(proc->cores[0]->exu->rf_fu_clockRate/proc->cores[0]->exu->clockRate); + initpower_coeff[INT_ACC] = + proc->cores[0]->get_coefficient_ialu_accesses() * + (proc->cores[0]->exu->rf_fu_clockRate / proc->cores[0]->exu->clockRate); - if(tot_fpu_accesses != 0){ - initpower_coeff[FP_ACC]= fp_coeff * sample_perf_counters[FP_ACC]/tot_fpu_accesses; - initpower_coeff[DP_ACC]= fp_coeff * sample_perf_counters[DP_ACC]/tot_fpu_accesses; - } - else{ - initpower_coeff[FP_ACC]= 0; - initpower_coeff[DP_ACC]= 0; + if (tot_fpu_accesses != 0) { + initpower_coeff[FP_ACC] = + fp_coeff * sample_perf_counters[FP_ACC] / tot_fpu_accesses; + initpower_coeff[DP_ACC] = + fp_coeff * sample_perf_counters[DP_ACC] / tot_fpu_accesses; + } else { + initpower_coeff[FP_ACC] = 0; + initpower_coeff[DP_ACC] = 0; } - if(tot_sfu_accesses != 0){ - initpower_coeff[INT_MUL24_ACC]= sfu_coeff * sample_perf_counters[INT_MUL24_ACC]/tot_sfu_accesses; - initpower_coeff[INT_MUL32_ACC]= sfu_coeff * sample_perf_counters[INT_MUL32_ACC]/tot_sfu_accesses; - initpower_coeff[INT_MUL_ACC]= sfu_coeff * sample_perf_counters[INT_MUL_ACC]/tot_sfu_accesses; - initpower_coeff[INT_DIV_ACC]= sfu_coeff * sample_perf_counters[INT_DIV_ACC]/tot_sfu_accesses; - initpower_coeff[DP_MUL_ACC]= sfu_coeff * sample_perf_counters[DP_MUL_ACC]/tot_sfu_accesses; - initpower_coeff[DP_DIV_ACC]= sfu_coeff * sample_perf_counters[DP_DIV_ACC]/tot_sfu_accesses; - initpower_coeff[FP_MUL_ACC]= sfu_coeff * sample_perf_counters[FP_MUL_ACC]/tot_sfu_accesses; - initpower_coeff[FP_DIV_ACC]= sfu_coeff * sample_perf_counters[FP_DIV_ACC]/tot_sfu_accesses; - initpower_coeff[FP_SQRT_ACC]= sfu_coeff * sample_perf_counters[FP_SQRT_ACC]/tot_sfu_accesses; - initpower_coeff[FP_LG_ACC]= sfu_coeff * sample_perf_counters[FP_LG_ACC]/tot_sfu_accesses; - initpower_coeff[FP_SIN_ACC]= sfu_coeff * sample_perf_counters[FP_SIN_ACC]/tot_sfu_accesses; - initpower_coeff[FP_EXP_ACC]= sfu_coeff * sample_perf_counters[FP_EXP_ACC]/tot_sfu_accesses; - initpower_coeff[TENSOR_ACC]= sfu_coeff * sample_perf_counters[TENSOR_ACC]/tot_sfu_accesses; - initpower_coeff[TEX_ACC]= sfu_coeff * sample_perf_counters[TEX_ACC]/tot_sfu_accesses; - } - else{ - initpower_coeff[INT_MUL24_ACC]= 0; - initpower_coeff[INT_MUL32_ACC]= 0; - initpower_coeff[INT_MUL_ACC]= 0; - initpower_coeff[INT_DIV_ACC]= 0; - initpower_coeff[DP_MUL_ACC]= 0; - initpower_coeff[DP_DIV_ACC]= 0; - initpower_coeff[FP_MUL_ACC]= 0; - initpower_coeff[FP_DIV_ACC]= 0; - initpower_coeff[FP_SQRT_ACC]= 0; - initpower_coeff[FP_LG_ACC]= 0; - initpower_coeff[FP_SIN_ACC]= 0; - initpower_coeff[FP_EXP_ACC]= 0; - initpower_coeff[TENSOR_ACC]= 0; - initpower_coeff[TEX_ACC]= 0; + if (tot_sfu_accesses != 0) { + initpower_coeff[INT_MUL24_ACC] = + sfu_coeff * sample_perf_counters[INT_MUL24_ACC] / tot_sfu_accesses; + initpower_coeff[INT_MUL32_ACC] = + sfu_coeff * sample_perf_counters[INT_MUL32_ACC] / tot_sfu_accesses; + initpower_coeff[INT_MUL_ACC] = + sfu_coeff * sample_perf_counters[INT_MUL_ACC] / tot_sfu_accesses; + initpower_coeff[INT_DIV_ACC] = + sfu_coeff * sample_perf_counters[INT_DIV_ACC] / tot_sfu_accesses; + initpower_coeff[DP_MUL_ACC] = + sfu_coeff * sample_perf_counters[DP_MUL_ACC] / tot_sfu_accesses; + initpower_coeff[DP_DIV_ACC] = + sfu_coeff * sample_perf_counters[DP_DIV_ACC] / tot_sfu_accesses; + initpower_coeff[FP_MUL_ACC] = + sfu_coeff * sample_perf_counters[FP_MUL_ACC] / tot_sfu_accesses; + initpower_coeff[FP_DIV_ACC] = + sfu_coeff * sample_perf_counters[FP_DIV_ACC] / tot_sfu_accesses; + initpower_coeff[FP_SQRT_ACC] = + sfu_coeff * sample_perf_counters[FP_SQRT_ACC] / tot_sfu_accesses; + initpower_coeff[FP_LG_ACC] = + sfu_coeff * sample_perf_counters[FP_LG_ACC] / tot_sfu_accesses; + initpower_coeff[FP_SIN_ACC] = + sfu_coeff * sample_perf_counters[FP_SIN_ACC] / tot_sfu_accesses; + initpower_coeff[FP_EXP_ACC] = + sfu_coeff * sample_perf_counters[FP_EXP_ACC] / tot_sfu_accesses; + initpower_coeff[TENSOR_ACC] = + sfu_coeff * sample_perf_counters[TENSOR_ACC] / tot_sfu_accesses; + initpower_coeff[TEX_ACC] = + sfu_coeff * sample_perf_counters[TEX_ACC] / tot_sfu_accesses; + } else { + initpower_coeff[INT_MUL24_ACC] = 0; + initpower_coeff[INT_MUL32_ACC] = 0; + initpower_coeff[INT_MUL_ACC] = 0; + initpower_coeff[INT_DIV_ACC] = 0; + initpower_coeff[DP_MUL_ACC] = 0; + initpower_coeff[DP_DIV_ACC] = 0; + initpower_coeff[FP_MUL_ACC] = 0; + initpower_coeff[FP_DIV_ACC] = 0; + initpower_coeff[FP_SQRT_ACC] = 0; + initpower_coeff[FP_LG_ACC] = 0; + initpower_coeff[FP_SIN_ACC] = 0; + initpower_coeff[FP_EXP_ACC] = 0; + initpower_coeff[TENSOR_ACC] = 0; + initpower_coeff[TEX_ACC] = 0; } - effpower_coeff[INT_ACC]= initpower_coeff[INT_ACC]; - effpower_coeff[FP_ACC]= initpower_coeff[FP_ACC]; - effpower_coeff[DP_ACC]= initpower_coeff[DP_ACC]; - effpower_coeff[INT_MUL24_ACC]= initpower_coeff[INT_MUL24_ACC]; - effpower_coeff[INT_MUL32_ACC]= initpower_coeff[INT_MUL32_ACC]; - effpower_coeff[INT_MUL_ACC]= initpower_coeff[INT_MUL_ACC]; - effpower_coeff[INT_DIV_ACC]= initpower_coeff[INT_DIV_ACC]; - effpower_coeff[DP_MUL_ACC]= initpower_coeff[DP_MUL_ACC]; - effpower_coeff[DP_DIV_ACC]= initpower_coeff[DP_DIV_ACC]; - effpower_coeff[FP_MUL_ACC]= initpower_coeff[FP_MUL_ACC]; - effpower_coeff[FP_DIV_ACC]= initpower_coeff[FP_DIV_ACC]; - effpower_coeff[FP_SQRT_ACC]= initpower_coeff[FP_SQRT_ACC]; - effpower_coeff[FP_LG_ACC]= initpower_coeff[FP_LG_ACC]; - effpower_coeff[FP_SIN_ACC]= initpower_coeff[FP_SIN_ACC]; - effpower_coeff[FP_EXP_ACC]= initpower_coeff[FP_EXP_ACC]; - effpower_coeff[TENSOR_ACC]= initpower_coeff[TENSOR_ACC]; - effpower_coeff[TEX_ACC]= initpower_coeff[TEX_ACC]; + effpower_coeff[INT_ACC] = initpower_coeff[INT_ACC]; + effpower_coeff[FP_ACC] = initpower_coeff[FP_ACC]; + effpower_coeff[DP_ACC] = initpower_coeff[DP_ACC]; + effpower_coeff[INT_MUL24_ACC] = initpower_coeff[INT_MUL24_ACC]; + effpower_coeff[INT_MUL32_ACC] = initpower_coeff[INT_MUL32_ACC]; + effpower_coeff[INT_MUL_ACC] = initpower_coeff[INT_MUL_ACC]; + effpower_coeff[INT_DIV_ACC] = initpower_coeff[INT_DIV_ACC]; + effpower_coeff[DP_MUL_ACC] = initpower_coeff[DP_MUL_ACC]; + effpower_coeff[DP_DIV_ACC] = initpower_coeff[DP_DIV_ACC]; + effpower_coeff[FP_MUL_ACC] = initpower_coeff[FP_MUL_ACC]; + effpower_coeff[FP_DIV_ACC] = initpower_coeff[FP_DIV_ACC]; + effpower_coeff[FP_SQRT_ACC] = initpower_coeff[FP_SQRT_ACC]; + effpower_coeff[FP_LG_ACC] = initpower_coeff[FP_LG_ACC]; + effpower_coeff[FP_SIN_ACC] = initpower_coeff[FP_SIN_ACC]; + effpower_coeff[FP_EXP_ACC] = initpower_coeff[FP_EXP_ACC]; + effpower_coeff[TENSOR_ACC] = initpower_coeff[TENSOR_ACC]; + effpower_coeff[TEX_ACC] = initpower_coeff[TEX_ACC]; - initpower_coeff[NOC_A]=proc->get_coefficient_noc_accesses(); - effpower_coeff[NOC_A]=initpower_coeff[NOC_A]*p->sys.scaling_coefficients[NOC_A]; + initpower_coeff[NOC_A] = proc->get_coefficient_noc_accesses(); + effpower_coeff[NOC_A] = + initpower_coeff[NOC_A] * p->sys.scaling_coefficients[NOC_A]; - //const_dynamic_power=proc->get_const_dynamic_power()/(proc->cores[0]->executionTime); + // const_dynamic_power=proc->get_const_dynamic_power()/(proc->cores[0]->executionTime); - for(unsigned i=0; i<num_perf_counters; i++){ - initpower_coeff[i]/=(proc->cores[0]->executionTime); - effpower_coeff[i]/=(proc->cores[0]->executionTime); + for (unsigned i = 0; i < num_perf_counters; i++) { + initpower_coeff[i] /= (proc->cores[0]->executionTime); + effpower_coeff[i] /= (proc->cores[0]->executionTime); } } -double gpgpu_sim_wrapper::calculate_static_power(){ - double int_accesses = initpower_coeff[INT_ACC] + initpower_coeff[INT_MUL24_ACC] + initpower_coeff[INT_MUL32_ACC] + initpower_coeff[INT_MUL_ACC] + initpower_coeff[INT_DIV_ACC]; - double int_add_accesses = initpower_coeff[INT_ACC]; - double int_mul_accesses = initpower_coeff[INT_MUL24_ACC] + initpower_coeff[INT_MUL32_ACC] + initpower_coeff[INT_MUL_ACC] + initpower_coeff[INT_DIV_ACC]; - double fp_accesses = initpower_coeff[FP_ACC] + initpower_coeff[FP_MUL_ACC] + initpower_coeff[FP_DIV_ACC]; - double dp_accesses = initpower_coeff[DP_ACC] + initpower_coeff[DP_MUL_ACC] + initpower_coeff[DP_DIV_ACC]; - double sfu_accesses = initpower_coeff[FP_SQRT_ACC] + initpower_coeff[FP_LG_ACC] + initpower_coeff[FP_SIN_ACC] + initpower_coeff[FP_EXP_ACC]; - double tensor_accesses = initpower_coeff[TENSOR_ACC]; - double tex_accesses = initpower_coeff[TEX_ACC]; - double total_static_power = 0.0; - double base_static_power = 0.0; - double lane_static_power = 0.0; - double per_active_core = (num_cores - num_idle_cores)/num_cores; - +double gpgpu_sim_wrapper::calculate_static_power() { + double int_accesses = + initpower_coeff[INT_ACC] + initpower_coeff[INT_MUL24_ACC] + + initpower_coeff[INT_MUL32_ACC] + initpower_coeff[INT_MUL_ACC] + + initpower_coeff[INT_DIV_ACC]; + double int_add_accesses = initpower_coeff[INT_ACC]; + double int_mul_accesses = + initpower_coeff[INT_MUL24_ACC] + initpower_coeff[INT_MUL32_ACC] + + initpower_coeff[INT_MUL_ACC] + initpower_coeff[INT_DIV_ACC]; + double fp_accesses = initpower_coeff[FP_ACC] + initpower_coeff[FP_MUL_ACC] + + initpower_coeff[FP_DIV_ACC]; + double dp_accesses = initpower_coeff[DP_ACC] + initpower_coeff[DP_MUL_ACC] + + initpower_coeff[DP_DIV_ACC]; + double sfu_accesses = + initpower_coeff[FP_SQRT_ACC] + initpower_coeff[FP_LG_ACC] + + initpower_coeff[FP_SIN_ACC] + initpower_coeff[FP_EXP_ACC]; + double tensor_accesses = initpower_coeff[TENSOR_ACC]; + double tex_accesses = initpower_coeff[TEX_ACC]; + double total_static_power = 0.0; + double base_static_power = 0.0; + double lane_static_power = 0.0; + double per_active_core = (num_cores - num_idle_cores) / num_cores; - double l1_accesses = initpower_coeff[DC_RH] + initpower_coeff[DC_RM] + initpower_coeff[DC_WH] + initpower_coeff[DC_WM]; - double l2_accesses = initpower_coeff[L2_RH] + initpower_coeff[L2_RM] + initpower_coeff[L2_WH] + initpower_coeff[L2_WM]; - double shared_accesses = initpower_coeff[SHRD_ACC]; + double l1_accesses = initpower_coeff[DC_RH] + initpower_coeff[DC_RM] + + initpower_coeff[DC_WH] + initpower_coeff[DC_WM]; + double l2_accesses = initpower_coeff[L2_RH] + initpower_coeff[L2_RM] + + initpower_coeff[L2_WH] + initpower_coeff[L2_WM]; + double shared_accesses = initpower_coeff[SHRD_ACC]; + if (avg_threads_per_warp == + 0) { // no functional unit threads, check for memory or a 'LIGHT_SM' + if (l1_accesses != 0.0) + return (p->sys.static_l1_flane * per_active_core); + else if (shared_accesses != 0.0) + return (p->sys.static_shared_flane * per_active_core); + else if (l2_accesses != 0.0) + return (p->sys.static_l2_flane * per_active_core); + else // LIGHT_SM + return (p->sys.static_light_flane * + per_active_core); // return LIGHT_SM base static power + } - if(avg_threads_per_warp == 0){ //no functional unit threads, check for memory or a 'LIGHT_SM' - if(l1_accesses != 0.0) - return (p->sys.static_l1_flane*per_active_core); - else if(shared_accesses != 0.0) - return (p->sys.static_shared_flane*per_active_core); - else if(l2_accesses != 0.0) - return (p->sys.static_l2_flane*per_active_core); - else //LIGHT_SM - return (p->sys.static_light_flane*per_active_core); //return LIGHT_SM base static power - } - - /* using a linear model for thread divergence */ - if((int_accesses != 0.0) && (fp_accesses != 0.0) && (dp_accesses != 0.0) && (sfu_accesses == 0.0) && (tensor_accesses == 0.0) && (tex_accesses == 0.0)){ - /* INT_FP_DP */ - base_static_power = p->sys.static_cat3_flane; - lane_static_power = p->sys.static_cat3_addlane; - } + /* using a linear model for thread divergence */ + if ((int_accesses != 0.0) && (fp_accesses != 0.0) && (dp_accesses != 0.0) && + (sfu_accesses == 0.0) && (tensor_accesses == 0.0) && + (tex_accesses == 0.0)) { + /* INT_FP_DP */ + base_static_power = p->sys.static_cat3_flane; + lane_static_power = p->sys.static_cat3_addlane; + } - else if((int_accesses != 0.0) && (fp_accesses != 0.0) && (dp_accesses == 0.0) && (sfu_accesses == 0.0) && (tensor_accesses != 0.0) && (tex_accesses == 0.0)){ - /* INT_FP_TENSOR */ - base_static_power = p->sys.static_cat6_flane; - lane_static_power = p->sys.static_cat6_addlane; - } + else if ((int_accesses != 0.0) && (fp_accesses != 0.0) && + (dp_accesses == 0.0) && (sfu_accesses == 0.0) && + (tensor_accesses != 0.0) && (tex_accesses == 0.0)) { + /* INT_FP_TENSOR */ + base_static_power = p->sys.static_cat6_flane; + lane_static_power = p->sys.static_cat6_addlane; + } - else if((int_accesses != 0.0) && (fp_accesses != 0.0) && (dp_accesses == 0.0) && (sfu_accesses != 0.0) && (tensor_accesses == 0.0) && (tex_accesses == 0.0)){ - /* INT_FP_SFU */ - base_static_power = p->sys.static_cat4_flane; - lane_static_power = p->sys.static_cat4_addlane; - } + else if ((int_accesses != 0.0) && (fp_accesses != 0.0) && + (dp_accesses == 0.0) && (sfu_accesses != 0.0) && + (tensor_accesses == 0.0) && (tex_accesses == 0.0)) { + /* INT_FP_SFU */ + base_static_power = p->sys.static_cat4_flane; + lane_static_power = p->sys.static_cat4_addlane; + } - else if((int_accesses != 0.0) && (fp_accesses != 0.0) && (dp_accesses == 0.0) && (sfu_accesses == 0.0) && (tensor_accesses == 0.0) && (tex_accesses != 0.0)){ - /* INT_FP_TEX */ - base_static_power = p->sys.static_cat5_flane; - lane_static_power = p->sys.static_cat5_addlane; - } + else if ((int_accesses != 0.0) && (fp_accesses != 0.0) && + (dp_accesses == 0.0) && (sfu_accesses == 0.0) && + (tensor_accesses == 0.0) && (tex_accesses != 0.0)) { + /* INT_FP_TEX */ + base_static_power = p->sys.static_cat5_flane; + lane_static_power = p->sys.static_cat5_addlane; + } - else if((int_accesses != 0.0) && (fp_accesses != 0.0) && (dp_accesses == 0.0) && (sfu_accesses == 0.0) && (tensor_accesses == 0.0) && (tex_accesses == 0.0)){ - /* INT_FP */ - base_static_power = p->sys.static_cat2_flane; - lane_static_power = p->sys.static_cat2_addlane; - } + else if ((int_accesses != 0.0) && (fp_accesses != 0.0) && + (dp_accesses == 0.0) && (sfu_accesses == 0.0) && + (tensor_accesses == 0.0) && (tex_accesses == 0.0)) { + /* INT_FP */ + base_static_power = p->sys.static_cat2_flane; + lane_static_power = p->sys.static_cat2_addlane; + } - else if((int_accesses != 0.0) && (fp_accesses == 0.0) && (dp_accesses == 0.0) && (sfu_accesses == 0.0) && (tensor_accesses == 0.0) && (tex_accesses == 0.0)){ - /* INT */ - /* Seperating INT_ADD only and INT_MUL only from mix of INT instructions */ - if((int_add_accesses != 0.0) && (int_mul_accesses == 0.0)){ //INT_ADD - base_static_power = p->sys.static_intadd_flane; - lane_static_power = p->sys.static_intadd_addlane; - } - else if((int_add_accesses == 0.0) && (int_mul_accesses != 0.0)){ //INT_MUL - base_static_power = p->sys.static_intmul_flane; - lane_static_power = p->sys.static_intmul_addlane; - } - else{ //INT_ADD+MUL - base_static_power = p->sys.static_cat1_flane; - lane_static_power = p->sys.static_cat1_addlane; - } - } + else if ((int_accesses != 0.0) && (fp_accesses == 0.0) && + (dp_accesses == 0.0) && (sfu_accesses == 0.0) && + (tensor_accesses == 0.0) && (tex_accesses == 0.0)) { + /* INT */ + /* Seperating INT_ADD only and INT_MUL only from mix of INT instructions */ + if ((int_add_accesses != 0.0) && (int_mul_accesses == 0.0)) { // INT_ADD + base_static_power = p->sys.static_intadd_flane; + lane_static_power = p->sys.static_intadd_addlane; + } else if ((int_add_accesses == 0.0) && + (int_mul_accesses != 0.0)) { // INT_MUL + base_static_power = p->sys.static_intmul_flane; + lane_static_power = p->sys.static_intmul_addlane; + } else { // INT_ADD+MUL + base_static_power = p->sys.static_cat1_flane; + lane_static_power = p->sys.static_cat1_addlane; + } + } - else if((int_accesses == 0.0) && (fp_accesses == 0.0) && (dp_accesses == 0.0) && (sfu_accesses == 0.0) && (tensor_accesses == 0.0) && (tex_accesses == 0.0)){ - /* LIGHT_SM or memory only sample */ - lane_static_power = 0.0; //addlane static power is 0 for l1/l2/shared memory only accesses - if(l1_accesses != 0.0) - base_static_power = p->sys.static_l1_flane; - else if(shared_accesses != 0.0) - base_static_power = p->sys.static_shared_flane; - else if(l2_accesses != 0.0) - base_static_power = p->sys.static_l2_flane; - else{ - base_static_power = p->sys.static_light_flane; - lane_static_power = p->sys.static_light_addlane; - } - } - else{ - base_static_power = p->sys.static_geomean_flane; //GEOMEAN except LIGHT_SM if we don't fall into any of the categories above - lane_static_power = p->sys.static_geomean_addlane; - } + else if ((int_accesses == 0.0) && (fp_accesses == 0.0) && + (dp_accesses == 0.0) && (sfu_accesses == 0.0) && + (tensor_accesses == 0.0) && (tex_accesses == 0.0)) { + /* LIGHT_SM or memory only sample */ + lane_static_power = + 0.0; // addlane static power is 0 for l1/l2/shared memory only accesses + if (l1_accesses != 0.0) + base_static_power = p->sys.static_l1_flane; + else if (shared_accesses != 0.0) + base_static_power = p->sys.static_shared_flane; + else if (l2_accesses != 0.0) + base_static_power = p->sys.static_l2_flane; + else { + base_static_power = p->sys.static_light_flane; + lane_static_power = p->sys.static_light_addlane; + } + } else { + base_static_power = + p->sys.static_geomean_flane; // GEOMEAN except LIGHT_SM if we don't + // fall into any of the categories above + lane_static_power = p->sys.static_geomean_addlane; + } - total_static_power = base_static_power + (((double)avg_threads_per_warp-1.0)*lane_static_power); //Linear Model - return (total_static_power*per_active_core); + total_static_power = + base_static_power + (((double)avg_threads_per_warp - 1.0) * + lane_static_power); // Linear Model + return (total_static_power * per_active_core); } -void gpgpu_sim_wrapper::update_components_power() -{ - +void gpgpu_sim_wrapper::update_components_power() { update_coefficients(); - proc_power=proc->rt_power.readOp.dynamic; - sample_cmp_pwr[IBP]=(proc->cores[0]->ifu->IB->rt_power.readOp.dynamic - +proc->cores[0]->ifu->IB->rt_power.writeOp.dynamic - +proc->cores[0]->ifu->ID_misc->rt_power.readOp.dynamic - +proc->cores[0]->ifu->ID_operand->rt_power.readOp.dynamic - +proc->cores[0]->ifu->ID_inst->rt_power.readOp.dynamic)/(proc->cores[0]->executionTime); + proc_power = proc->rt_power.readOp.dynamic; + sample_cmp_pwr[IBP] = + (proc->cores[0]->ifu->IB->rt_power.readOp.dynamic + + proc->cores[0]->ifu->IB->rt_power.writeOp.dynamic + + proc->cores[0]->ifu->ID_misc->rt_power.readOp.dynamic + + proc->cores[0]->ifu->ID_operand->rt_power.readOp.dynamic + + proc->cores[0]->ifu->ID_inst->rt_power.readOp.dynamic) / + (proc->cores[0]->executionTime); - sample_cmp_pwr[ICP]=proc->cores[0]->ifu->icache.rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[ICP] = proc->cores[0]->ifu->icache.rt_power.readOp.dynamic / + (proc->cores[0]->executionTime); - sample_cmp_pwr[DCP]=proc->cores[0]->lsu->dcache.rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[DCP] = proc->cores[0]->lsu->dcache.rt_power.readOp.dynamic / + (proc->cores[0]->executionTime); - sample_cmp_pwr[TCP]=proc->cores[0]->lsu->tcache.rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[TCP] = proc->cores[0]->lsu->tcache.rt_power.readOp.dynamic / + (proc->cores[0]->executionTime); - sample_cmp_pwr[CCP]=proc->cores[0]->lsu->ccache.rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[CCP] = proc->cores[0]->lsu->ccache.rt_power.readOp.dynamic / + (proc->cores[0]->executionTime); - sample_cmp_pwr[SHRDP]=proc->cores[0]->lsu->sharedmemory.rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[SHRDP] = + proc->cores[0]->lsu->sharedmemory.rt_power.readOp.dynamic / + (proc->cores[0]->executionTime); - sample_cmp_pwr[RFP]=(proc->cores[0]->exu->rfu->rt_power.readOp.dynamic/(proc->cores[0]->executionTime)) - *(proc->cores[0]->exu->rf_fu_clockRate/proc->cores[0]->exu->clockRate); + sample_cmp_pwr[RFP] = + (proc->cores[0]->exu->rfu->rt_power.readOp.dynamic / + (proc->cores[0]->executionTime)) * + (proc->cores[0]->exu->rf_fu_clockRate / proc->cores[0]->exu->clockRate); - double sample_fp_pwr = (proc->cores[0]->exu->fp_u->rt_power.readOp.dynamic/(proc->cores[0]->executionTime)); + double sample_fp_pwr = (proc->cores[0]->exu->fp_u->rt_power.readOp.dynamic / + (proc->cores[0]->executionTime)); - double sample_sfu_pwr = (proc->cores[0]->exu->mul->rt_power.readOp.dynamic/(proc->cores[0]->executionTime)); + double sample_sfu_pwr = (proc->cores[0]->exu->mul->rt_power.readOp.dynamic / + (proc->cores[0]->executionTime)); - sample_cmp_pwr[INTP]=(proc->cores[0]->exu->exeu->rt_power.readOp.dynamic/(proc->cores[0]->executionTime)) - *(proc->cores[0]->exu->rf_fu_clockRate/proc->cores[0]->exu->clockRate); + sample_cmp_pwr[INTP] = + (proc->cores[0]->exu->exeu->rt_power.readOp.dynamic / + (proc->cores[0]->executionTime)) * + (proc->cores[0]->exu->rf_fu_clockRate / proc->cores[0]->exu->clockRate); - - if(tot_fpu_accesses != 0){ - sample_cmp_pwr[FPUP]= sample_fp_pwr * sample_perf_counters[FP_ACC]/tot_fpu_accesses; - sample_cmp_pwr[DPUP]= sample_fp_pwr * sample_perf_counters[DP_ACC]/tot_fpu_accesses; - } - else{ - sample_cmp_pwr[FPUP]= 0; - sample_cmp_pwr[DPUP]= 0; - } - if(tot_sfu_accesses != 0){ - sample_cmp_pwr[INT_MUL24P]= sample_sfu_pwr * sample_perf_counters[INT_MUL24_ACC]/tot_sfu_accesses; - sample_cmp_pwr[INT_MUL32P]= sample_sfu_pwr * sample_perf_counters[INT_MUL32_ACC]/tot_sfu_accesses; - sample_cmp_pwr[INT_MULP]= sample_sfu_pwr * sample_perf_counters[INT_MUL_ACC]/tot_sfu_accesses; - sample_cmp_pwr[INT_DIVP]= sample_sfu_pwr * sample_perf_counters[INT_DIV_ACC]/tot_sfu_accesses; - sample_cmp_pwr[FP_MULP]= sample_sfu_pwr * sample_perf_counters[FP_MUL_ACC]/tot_sfu_accesses; - sample_cmp_pwr[FP_DIVP]= sample_sfu_pwr * sample_perf_counters[FP_DIV_ACC]/tot_sfu_accesses; - sample_cmp_pwr[FP_SQRTP]= sample_sfu_pwr * sample_perf_counters[FP_SQRT_ACC]/tot_sfu_accesses; - sample_cmp_pwr[FP_LGP]= sample_sfu_pwr * sample_perf_counters[FP_LG_ACC]/tot_sfu_accesses; - sample_cmp_pwr[FP_SINP]= sample_sfu_pwr * sample_perf_counters[FP_SIN_ACC]/tot_sfu_accesses; - sample_cmp_pwr[FP_EXP]= sample_sfu_pwr * sample_perf_counters[FP_EXP_ACC]/tot_sfu_accesses; - sample_cmp_pwr[DP_MULP]= sample_sfu_pwr * sample_perf_counters[DP_MUL_ACC]/tot_sfu_accesses; - sample_cmp_pwr[DP_DIVP]= sample_sfu_pwr * sample_perf_counters[DP_DIV_ACC]/tot_sfu_accesses; - sample_cmp_pwr[TENSORP]= sample_sfu_pwr * sample_perf_counters[TENSOR_ACC]/tot_sfu_accesses; - sample_cmp_pwr[TEXP]= sample_sfu_pwr * sample_perf_counters[TEX_ACC]/tot_sfu_accesses; + if (tot_fpu_accesses != 0) { + sample_cmp_pwr[FPUP] = + sample_fp_pwr * sample_perf_counters[FP_ACC] / tot_fpu_accesses; + sample_cmp_pwr[DPUP] = + sample_fp_pwr * sample_perf_counters[DP_ACC] / tot_fpu_accesses; + } else { + sample_cmp_pwr[FPUP] = 0; + sample_cmp_pwr[DPUP] = 0; } - else{ - sample_cmp_pwr[INT_MUL24P]= 0; - sample_cmp_pwr[INT_MUL32P]= 0; - sample_cmp_pwr[INT_MULP]= 0; - sample_cmp_pwr[INT_DIVP]= 0; - sample_cmp_pwr[FP_MULP]= 0; - sample_cmp_pwr[FP_DIVP]= 0; - sample_cmp_pwr[FP_SQRTP]= 0; - sample_cmp_pwr[FP_LGP]= 0; - sample_cmp_pwr[FP_SINP]= 0; - sample_cmp_pwr[FP_EXP]= 0; - sample_cmp_pwr[DP_MULP]= 0; - sample_cmp_pwr[DP_DIVP]= 0; - sample_cmp_pwr[TENSORP]= 0; - sample_cmp_pwr[TEXP]= 0; + if (tot_sfu_accesses != 0) { + sample_cmp_pwr[INT_MUL24P] = + sample_sfu_pwr * sample_perf_counters[INT_MUL24_ACC] / tot_sfu_accesses; + sample_cmp_pwr[INT_MUL32P] = + sample_sfu_pwr * sample_perf_counters[INT_MUL32_ACC] / tot_sfu_accesses; + sample_cmp_pwr[INT_MULP] = + sample_sfu_pwr * sample_perf_counters[INT_MUL_ACC] / tot_sfu_accesses; + sample_cmp_pwr[INT_DIVP] = + sample_sfu_pwr * sample_perf_counters[INT_DIV_ACC] / tot_sfu_accesses; + sample_cmp_pwr[FP_MULP] = + sample_sfu_pwr * sample_perf_counters[FP_MUL_ACC] / tot_sfu_accesses; + sample_cmp_pwr[FP_DIVP] = + sample_sfu_pwr * sample_perf_counters[FP_DIV_ACC] / tot_sfu_accesses; + sample_cmp_pwr[FP_SQRTP] = + sample_sfu_pwr * sample_perf_counters[FP_SQRT_ACC] / tot_sfu_accesses; + sample_cmp_pwr[FP_LGP] = + sample_sfu_pwr * sample_perf_counters[FP_LG_ACC] / tot_sfu_accesses; + sample_cmp_pwr[FP_SINP] = + sample_sfu_pwr * sample_perf_counters[FP_SIN_ACC] / tot_sfu_accesses; + sample_cmp_pwr[FP_EXP] = + sample_sfu_pwr * sample_perf_counters[FP_EXP_ACC] / tot_sfu_accesses; + sample_cmp_pwr[DP_MULP] = + sample_sfu_pwr * sample_perf_counters[DP_MUL_ACC] / tot_sfu_accesses; + sample_cmp_pwr[DP_DIVP] = + sample_sfu_pwr * sample_perf_counters[DP_DIV_ACC] / tot_sfu_accesses; + sample_cmp_pwr[TENSORP] = + sample_sfu_pwr * sample_perf_counters[TENSOR_ACC] / tot_sfu_accesses; + sample_cmp_pwr[TEXP] = + sample_sfu_pwr * sample_perf_counters[TEX_ACC] / tot_sfu_accesses; + } else { + sample_cmp_pwr[INT_MUL24P] = 0; + sample_cmp_pwr[INT_MUL32P] = 0; + sample_cmp_pwr[INT_MULP] = 0; + sample_cmp_pwr[INT_DIVP] = 0; + sample_cmp_pwr[FP_MULP] = 0; + sample_cmp_pwr[FP_DIVP] = 0; + sample_cmp_pwr[FP_SQRTP] = 0; + sample_cmp_pwr[FP_LGP] = 0; + sample_cmp_pwr[FP_SINP] = 0; + sample_cmp_pwr[FP_EXP] = 0; + sample_cmp_pwr[DP_MULP] = 0; + sample_cmp_pwr[DP_DIVP] = 0; + sample_cmp_pwr[TENSORP] = 0; + sample_cmp_pwr[TEXP] = 0; } - sample_cmp_pwr[SCHEDP]=proc->cores[0]->exu->scheu->rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[SCHEDP] = proc->cores[0]->exu->scheu->rt_power.readOp.dynamic / + (proc->cores[0]->executionTime); - sample_cmp_pwr[L2CP]=(proc->XML->sys.number_of_L2s>0)? proc->l2array[0]->rt_power.readOp.dynamic/(proc->cores[0]->executionTime):0; + sample_cmp_pwr[L2CP] = (proc->XML->sys.number_of_L2s > 0) + ? proc->l2array[0]->rt_power.readOp.dynamic / + (proc->cores[0]->executionTime) + : 0; - sample_cmp_pwr[MCP]=(proc->mc->rt_power.readOp.dynamic-proc->mc->dram->rt_power.readOp.dynamic)/(proc->cores[0]->executionTime); + sample_cmp_pwr[MCP] = (proc->mc->rt_power.readOp.dynamic - + proc->mc->dram->rt_power.readOp.dynamic) / + (proc->cores[0]->executionTime); - sample_cmp_pwr[NOCP]=proc->nocs[0]->rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[NOCP] = + proc->nocs[0]->rt_power.readOp.dynamic / (proc->cores[0]->executionTime); - sample_cmp_pwr[DRAMP]=proc->mc->dram->rt_power.readOp.dynamic/(proc->cores[0]->executionTime); + sample_cmp_pwr[DRAMP] = + proc->mc->dram->rt_power.readOp.dynamic / (proc->cores[0]->executionTime); - sample_cmp_pwr[PIPEP]=proc->cores[0]->Pipeline_energy/(proc->cores[0]->executionTime); + sample_cmp_pwr[PIPEP] = + proc->cores[0]->Pipeline_energy / (proc->cores[0]->executionTime); - sample_cmp_pwr[IDLE_COREP]=proc->cores[0]->IdleCoreEnergy/(proc->cores[0]->executionTime); + sample_cmp_pwr[IDLE_COREP] = + proc->cores[0]->IdleCoreEnergy / (proc->cores[0]->executionTime); - // This constant dynamic power (e.g., clock power) part is estimated via regression model. - sample_cmp_pwr[CONSTP]=0; - sample_cmp_pwr[STATICP]=0; - // double cnst_dyn = proc->get_const_dynamic_power()/(proc->cores[0]->executionTime); - // // If the regression scaling term is greater than the recorded constant dynamic power - // // then use the difference (other portion already added to dynamic power). Else, + // This constant dynamic power (e.g., clock power) part is estimated via + // regression model. + sample_cmp_pwr[CONSTP] = 0; + sample_cmp_pwr[STATICP] = 0; + // double cnst_dyn = + // proc->get_const_dynamic_power()/(proc->cores[0]->executionTime); + // // If the regression scaling term is greater than the recorded constant + // dynamic power + // // then use the difference (other portion already added to dynamic power). + // Else, // // all the constant dynamic power is accounted for, add nothing. // if(p->sys.scaling_coefficients[constant_power] > cnst_dyn) - // sample_cmp_pwr[CONSTP] = (p->sys.scaling_coefficients[constant_power]-cnst_dyn); + // sample_cmp_pwr[CONSTP] = + // (p->sys.scaling_coefficients[constant_power]-cnst_dyn); sample_cmp_pwr[CONSTP] = p->sys.scaling_coefficients[constant_power]; sample_cmp_pwr[STATICP] = calculate_static_power(); - if(g_dvfs_enabled){ - double voltage_ratio = modeled_chip_voltage/p->sys.modeled_chip_voltage_ref; - sample_cmp_pwr[IDLE_COREP] *= voltage_ratio; // static power scaled by voltage_ratio - sample_cmp_pwr[STATICP] *= voltage_ratio; // static power scaled by voltage_ratio - for(unsigned i=0; i<num_pwr_cmps; i++){ - if((i != IDLE_COREP) && (i != STATICP)){ - sample_cmp_pwr[i] *= voltage_ratio*voltage_ratio; // dynamic power scaled by square of voltage_ratio - } - } + if (g_dvfs_enabled) { + double voltage_ratio = + modeled_chip_voltage / p->sys.modeled_chip_voltage_ref; + sample_cmp_pwr[IDLE_COREP] *= + voltage_ratio; // static power scaled by voltage_ratio + sample_cmp_pwr[STATICP] *= + voltage_ratio; // static power scaled by voltage_ratio + for (unsigned i = 0; i < num_pwr_cmps; i++) { + if ((i != IDLE_COREP) && (i != STATICP)) { + sample_cmp_pwr[i] *= + voltage_ratio * + voltage_ratio; // dynamic power scaled by square of voltage_ratio + } + } } - - proc_power+=sample_cmp_pwr[CONSTP]+sample_cmp_pwr[STATICP]; - if(!g_dvfs_enabled){ // sanity check will fail when voltage scaling is applied, fix later - double sum_pwr_cmp=0; - for(unsigned i=0; i<num_pwr_cmps; i++){ - sum_pwr_cmp+=sample_cmp_pwr[i]; - } - bool check=false; - check=sanity_check(sum_pwr_cmp,proc_power); - if(!check) - printf("sum_pwr_cmp %f : proc_power %f \n",sum_pwr_cmp,proc_power); - assert("Total Power does not equal the sum of the components\n" && (check)); + + proc_power += sample_cmp_pwr[CONSTP] + sample_cmp_pwr[STATICP]; + if (!g_dvfs_enabled) { // sanity check will fail when voltage scaling is + // applied, fix later + double sum_pwr_cmp = 0; + for (unsigned i = 0; i < num_pwr_cmps; i++) { + sum_pwr_cmp += sample_cmp_pwr[i]; + } + bool check = false; + check = sanity_check(sum_pwr_cmp, proc_power); + if (!check) + printf("sum_pwr_cmp %f : proc_power %f \n", sum_pwr_cmp, proc_power); + assert("Total Power does not equal the sum of the components\n" && (check)); } } @@ -993,13 +1111,12 @@ void gpgpu_sim_wrapper::print_power_kernel_stats( } powerfile << "gpu_avg_threads_per_warp = " - << avg_threads_per_warp_tot / (double)kernel_sample_count - << std::endl; + << avg_threads_per_warp_tot / (double)kernel_sample_count + << std::endl; for (unsigned i = 0; i < num_perf_counters; ++i) { powerfile << "gpu_tot_" << perf_count_label[i] << " = " - << kernel_cmp_perf_counters[i].avg - << std::endl; + << kernel_cmp_perf_counters[i].avg << std::endl; } powerfile << std::endl << "Kernel Maximum Power Data:" << std::endl; diff --git a/src/accelwattch/gpgpu_sim_wrapper.h b/src/accelwattch/gpgpu_sim_wrapper.h index 33c4b72..dd71d89 100644 --- a/src/accelwattch/gpgpu_sim_wrapper.h +++ b/src/accelwattch/gpgpu_sim_wrapper.h @@ -1,16 +1,17 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Ahmed ElTantawy, Vijay Kandiah, Nikos Hardavellas -// The University of British Columbia, Northwestern University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Ahmed ElTantawy, +// Vijay Kandiah, Nikos Hardavellas The University of British Columbia, +// Northwestern University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -58,31 +59,32 @@ struct avg_max_min_counters { #ifndef COEFF_STRUCT #define COEFF_STRUCT -struct PowerscalingCoefficients{ - double int_coeff; - double int_mul_coeff; - double int_mul24_coeff; - double int_mul32_coeff; - double int_div_coeff; - double fp_coeff; - double dp_coeff; - double fp_mul_coeff; - double fp_div_coeff; - double dp_mul_coeff; - double dp_div_coeff; - double sqrt_coeff; - double log_coeff; - double sin_coeff; - double exp_coeff; - double tensor_coeff; - double tex_coeff; +struct PowerscalingCoefficients { + double int_coeff; + double int_mul_coeff; + double int_mul24_coeff; + double int_mul32_coeff; + double int_div_coeff; + double fp_coeff; + double dp_coeff; + double fp_mul_coeff; + double fp_div_coeff; + double dp_mul_coeff; + double dp_div_coeff; + double sqrt_coeff; + double log_coeff; + double sin_coeff; + double exp_coeff; + double tensor_coeff; + double tex_coeff; }; #endif class gpgpu_sim_wrapper { public: - gpgpu_sim_wrapper(bool power_simulation_enabled, char* xmlfile, int power_simulation_mode, bool dvfs_enabled); + gpgpu_sim_wrapper(bool power_simulation_enabled, char* xmlfile, + int power_simulation_mode, bool dvfs_enabled); ~gpgpu_sim_wrapper(); void init_mcpat(char* xmlfile, char* powerfile, char* power_trace_file, @@ -90,8 +92,9 @@ class gpgpu_sim_wrapper { bool power_sim_enabled, bool trace_enabled, bool steady_state_enabled, bool power_per_cycle_dump, double steady_power_deviation, double steady_min_period, - int zlevel, double init_val, int stat_sample_freq, int power_sim_mode, - bool dvfs_enabled, unsigned clock_freq, unsigned num_shaders); + int zlevel, double init_val, int stat_sample_freq, + int power_sim_mode, bool dvfs_enabled, unsigned clock_freq, + unsigned num_shaders); void init_mcpat_hw_mode(unsigned gpu_sim_cycle); void detect_print_steady_state(int position, double init_val); void close_files(); @@ -128,15 +131,15 @@ class gpgpu_sim_wrapper { void set_mem_ctrl_power(double reads, double writes, double dram_precharge); void set_exec_unit_power(double fpu_accesses, double ialu_accesses, double sfu_accesses); - void set_int_accesses(double ialu_accesses, double imul24_accesses, - double imul32_accesses, double imul_accesses, + void set_int_accesses(double ialu_accesses, double imul24_accesses, + double imul32_accesses, double imul_accesses, double idiv_accesses); - void set_dp_accesses(double dpu_accesses, double dpmul_accesses, + void set_dp_accesses(double dpu_accesses, double dpmul_accesses, double dpdiv_accesses); - void set_fp_accesses(double fpu_accesses, double fpmul_accesses, + void set_fp_accesses(double fpu_accesses, double fpmul_accesses, double fpdiv_accesses); - void set_trans_accesses(double sqrt_accesses, double log_accesses, - double sin_accesses, double exp_accesses); + void set_trans_accesses(double sqrt_accesses, double log_accesses, + double sin_accesses, double exp_accesses); void set_tensor_accesses(double tensor_accesses); void set_tex_accesses(double tex_accesses); void set_avg_active_threads(float active_threads); @@ -145,7 +148,7 @@ class gpgpu_sim_wrapper { void set_NoC_power(double noc_tot_acc); bool sanity_check(double a, double b); - PowerscalingCoefficients * get_scaling_coeffs(); + PowerscalingCoefficients* get_scaling_coeffs(); private: void print_steady_state(int position, double init_val); diff --git a/src/accelwattch/processor.cc b/src/accelwattch/processor.cc index 9e7f5b2..d5c7cdd 100644 --- a/src/accelwattch/processor.cc +++ b/src/accelwattch/processor.cc @@ -30,8 +30,8 @@ ***************************************************************************/ /******************************************************************** * Modified by: - * Jingwen Leng, University of Texas, Austin - * Syed Gilani, University of Wisconsin–Madison + * Jingwen Leng, University of Texas, Austin + * Syed Gilani, University of Wisconsin–Madison * Tayler Hetherington, University of British Columbia * Ahmed ElTantawy, University of British Columbia * Vijay Kandiah, Northwestern University diff --git a/src/accelwattch/xmlParser.cc b/src/accelwattch/xmlParser.cc index 8f49b39..780d2ad 100644 --- a/src/accelwattch/xmlParser.cc +++ b/src/accelwattch/xmlParser.cc @@ -1236,12 +1236,10 @@ static NextToken GetNextToken(XML *pXML, int *pcbToken, // Indicate we are dealing with text *pType = eTokenText; while ((ch = getNextChar(pXML))) { - if - XML_isSPACECHAR(ch) { - indexStart++; - break; - } - else if (ch == _CXML('/')) { + if XML_isSPACECHAR (ch) { + indexStart++; + break; + } else if (ch == _CXML('/')) { // If we find a slash then this maybe text or a short hand end tag // Peek at the next character to see it we have short hand end tag ch = pXML->lpXML[pXML->nIndex]; @@ -2193,15 +2191,15 @@ int XMLNode::CreateXMLStringR(XMLNodeData *pEntry, XMLSTR lpszMarker, nResult++; } } else - // If there are child nodes we need to terminate the start tag - if (nElementI) { - if (lpszMarker) lpszMarker[nResult - 1] = _CXML('>'); - if (nFormat >= 0) { - if (lpszMarker) lpszMarker[nResult] = _CXML('\n'); - nResult++; - } - } else - nResult--; + // If there are child nodes we need to terminate the start tag + if (nElementI) { + if (lpszMarker) lpszMarker[nResult - 1] = _CXML('>'); + if (nFormat >= 0) { + if (lpszMarker) lpszMarker[nResult] = _CXML('\n'); + nResult++; + } + } else + nResult--; } // Calculate the child format for when we recurse. This is used to diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 888cf77..833d33f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas, +// George L. Yuan, Jimmy Kwa, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -591,118 +592,118 @@ void ptx_instruction::set_fp_or_int_archop() { } } -void ptx_instruction::set_mul_div_or_other_archop(){ - sp_op=OTHER_OP; - if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){ - if(get_type() == F64_TYPE || get_type() == FF64_TYPE){ - switch(get_opcode()){ - case MUL_OP: - case MAD_OP: - case FMA_OP: - sp_op=DP_MUL_OP; - break; - case DIV_OP: - case REM_OP: - sp_op=DP_DIV_OP; - break; - case RCP_OP: - sp_op=DP_DIV_OP; - break; - case LG2_OP: - sp_op=FP_LG_OP; - break; - case RSQRT_OP: - case SQRT_OP: - sp_op=FP_SQRT_OP; - break; - case SIN_OP: - case COS_OP: - sp_op=FP_SIN_OP; - break; - case EX2_OP: - sp_op=FP_EXP_OP; - break; - case MMA_OP: - sp_op=TENSOR__OP; - break; - case TEX_OP: - sp_op=TEX__OP; - break; - default: - if((op==DP_OP) || (op==ALU_OP)) - sp_op=DP___OP; - break; - } +void ptx_instruction::set_mul_div_or_other_archop() { + sp_op = OTHER_OP; + if ((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && + (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && + (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && + (m_opcode != CALL_OP)) { + if (get_type() == F64_TYPE || get_type() == FF64_TYPE) { + switch (get_opcode()) { + case MUL_OP: + case MAD_OP: + case FMA_OP: + sp_op = DP_MUL_OP; + break; + case DIV_OP: + case REM_OP: + sp_op = DP_DIV_OP; + break; + case RCP_OP: + sp_op = DP_DIV_OP; + break; + case LG2_OP: + sp_op = FP_LG_OP; + break; + case RSQRT_OP: + case SQRT_OP: + sp_op = FP_SQRT_OP; + break; + case SIN_OP: + case COS_OP: + sp_op = FP_SIN_OP; + break; + case EX2_OP: + sp_op = FP_EXP_OP; + break; + case MMA_OP: + sp_op = TENSOR__OP; + break; + case TEX_OP: + sp_op = TEX__OP; + break; + default: + if ((op == DP_OP) || (op == ALU_OP)) sp_op = DP___OP; + break; } - else if(get_type()==F16_TYPE || get_type()==F32_TYPE){ - switch(get_opcode()){ - case MUL_OP: - case MAD_OP: - case FMA_OP: - sp_op=FP_MUL_OP; - break; - case DIV_OP: - case REM_OP: - sp_op=FP_DIV_OP; - break; - case RCP_OP: - sp_op=FP_DIV_OP; - break; - case LG2_OP: - sp_op=FP_LG_OP; - break; - case RSQRT_OP: - case SQRT_OP: - sp_op=FP_SQRT_OP; - break; - case SIN_OP: - case COS_OP: - sp_op=FP_SIN_OP; - break; - case EX2_OP: - sp_op=FP_EXP_OP; - break; - case MMA_OP: - sp_op=TENSOR__OP; - break; - case TEX_OP: - sp_op=TEX__OP; - break; - default: - if((op==SP_OP) || (op==ALU_OP)) - sp_op=FP__OP; - break; - } - }else { - switch(get_opcode()){ - case MUL24_OP: - case MAD24_OP: - sp_op=INT_MUL24_OP; - break; - case MUL_OP: - case MAD_OP: - case FMA_OP: - if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE) - sp_op=INT_MUL32_OP; - else - sp_op=INT_MUL_OP; - break; - case DIV_OP: - case REM_OP: - sp_op=INT_DIV_OP; - break; - case MMA_OP: - sp_op=TENSOR__OP; - break; - case TEX_OP: - sp_op=TEX__OP; - break; - default: - if((op==INTP_OP) || (op==ALU_OP)) - sp_op=INT__OP; - break; - } + } else if (get_type() == F16_TYPE || get_type() == F32_TYPE) { + switch (get_opcode()) { + case MUL_OP: + case MAD_OP: + case FMA_OP: + sp_op = FP_MUL_OP; + break; + case DIV_OP: + case REM_OP: + sp_op = FP_DIV_OP; + break; + case RCP_OP: + sp_op = FP_DIV_OP; + break; + case LG2_OP: + sp_op = FP_LG_OP; + break; + case RSQRT_OP: + case SQRT_OP: + sp_op = FP_SQRT_OP; + break; + case SIN_OP: + case COS_OP: + sp_op = FP_SIN_OP; + break; + case EX2_OP: + sp_op = FP_EXP_OP; + break; + case MMA_OP: + sp_op = TENSOR__OP; + break; + case TEX_OP: + sp_op = TEX__OP; + break; + default: + if ((op == SP_OP) || (op == ALU_OP)) sp_op = FP__OP; + break; } + } else { + switch (get_opcode()) { + case MUL24_OP: + case MAD24_OP: + sp_op = INT_MUL24_OP; + break; + case MUL_OP: + case MAD_OP: + case FMA_OP: + if (get_type() == U32_TYPE || get_type() == S32_TYPE || + get_type() == B32_TYPE) + sp_op = INT_MUL32_OP; + else + sp_op = INT_MUL_OP; + break; + case DIV_OP: + case REM_OP: + sp_op = INT_DIV_OP; + break; + case MMA_OP: + sp_op = TENSOR__OP; + break; + case TEX_OP: + sp_op = TEX__OP; + break; + default: + if ((op == INTP_OP) || (op == ALU_OP)) sp_op = INT__OP; + break; + } + } } } @@ -960,14 +961,16 @@ void ptx_instruction::set_opcode_and_latency() { break; } break; - case MUL24_OP: //MUL24 is performed on mul32 units (with additional instructions for bitmasking) on devices with compute capability >1.x - latency = int_latency[2]+1; - initiation_interval = int_init[2]+1; + case MUL24_OP: // MUL24 is performed on mul32 units (with additional + // instructions for bitmasking) on devices with compute + // capability >1.x + latency = int_latency[2] + 1; + initiation_interval = int_init[2] + 1; op = INTP_OP; break; case MAD24_OP: - latency = int_latency[3]+1; - initiation_interval = int_init[3]+1; + latency = int_latency[3] + 1; + initiation_interval = int_init[3] + 1; op = INTP_OP; break; case DIV_OP: @@ -1533,10 +1536,10 @@ void function_info::ptx_jit_config( filename_c.c_str()); assert(system(buff) != 0); FILE *fp = fopen(filename_c.c_str(), "r"); - char * ptr = fgets(buff, 1024, fp); - if(ptr == NULL ){ - printf("can't read file %s \n", filename_c.c_str()); - assert(0); + char *ptr = fgets(buff, 1024, fp); + if (ptr == NULL) { + printf("can't read file %s \n", filename_c.c_str()); + assert(0); } fclose(fp); std::string fn(buff); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4981c99..4792efc 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, // Jimmy Kwa, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -1948,7 +1949,7 @@ void mma_impl(const ptx_instruction *pI, core_t *core, warp_inst_t inst) { hex_val = (v[k / 2].s64 & 0xffff); else hex_val = ((v[k / 2].s64 & 0xffff0000) >> 16); - nw_v[k].f16 = *(reinterpret_cast<half*>(hex_val)); + nw_v[k].f16 = *(reinterpret_cast<half *>(hex_val)); } } if (!((operand_num == 3) && (type2 == F32_TYPE))) { @@ -3980,7 +3981,7 @@ void mad_def(const ptx_instruction *pI, ptx_thread_info *thread, fesetround(FE_TOWARDZERO); break; default: - //assert(0); + // assert(0); break; } d.f32 = a.f32 * b.f32 + c.f32; @@ -4326,7 +4327,7 @@ void mul_impl(const ptx_instruction *pI, ptx_thread_info *thread) { case S64_TYPE: t.s64 = a.s64 * b.s64; assert(!pI->is_wide()); - //assert(!pI->is_hi()); + // assert(!pI->is_hi()); d.s64 = t.s64; break; case U16_TYPE: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index f25f1d5..d309542 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, // George L. Yuan, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -1386,7 +1387,7 @@ ptx_instruction::ptx_instruction( case CS_OPTION: case LU_OPTION: case CV_OPTION: - case WB_OPTION: + case WB_OPTION: case WT_OPTION: m_cache_option = last_ptx_inst_option; break; @@ -1469,8 +1470,8 @@ std::string ptx_instruction::to_string() const { char buf[STR_SIZE]; unsigned used_bytes = 0; if (!is_label()) { - used_bytes += - snprintf(buf + used_bytes, STR_SIZE - used_bytes, " PC=0x%03llx ", m_PC); + used_bytes += snprintf(buf + used_bytes, STR_SIZE - used_bytes, + " PC=0x%03llx ", m_PC); } else { used_bytes += snprintf(buf + used_bytes, STR_SIZE - used_bytes, " "); diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 7ba7171..8b1f19c 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1248,7 +1248,7 @@ class function_info { const ptx_version &get_ptx_version() const { return m_symtab->get_ptx_version(); } - virtual ~function_info(){} + virtual ~function_info() {} unsigned get_sm_target() const { return m_symtab->get_sm_target(); } bool is_extern() const { return m_extern; } void set_name(const char *name) { m_name = name; } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 6503499..2a548ee 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -369,7 +369,8 @@ static void print_reg(FILE *fp, std::string name, ptx_reg_t value, fprintf(fp, ".u64 %llu [0x%llx]\n", value.u64, value.u64); break; case F16_TYPE: - fprintf(fp, ".f16 %f [0x%04x]\n", static_cast<float>(value.f16), (unsigned)value.u16); + fprintf(fp, ".f16 %f [0x%04x]\n", static_cast<float>(value.f16), + (unsigned)value.u16); break; case F32_TYPE: fprintf(fp, ".f32 %.15lf [0x%08x]\n", value.f32, value.u32); diff --git a/src/debug.cc b/src/debug.cc index e23ffd4..8cc5e1f 100644 --- a/src/debug.cc +++ b/src/debug.cc @@ -124,7 +124,7 @@ void gpgpu_sim::gpgpu_debug() { fflush(stdout); char line[1024]; - char * ptr = fgets(line, 1024, stdin); + char *ptr = fgets(line, 1024, stdin); char *tok = strtok(line, " \t\n"); if (!strcmp(tok, "dp")) { @@ -137,7 +137,7 @@ void gpgpu_sim::gpgpu_debug() { } else if (!strcmp(tok, "q") || !strcmp(tok, "quit")) { printf("\nreally quit GPGPU-Sim (y/n)?\n"); ptr = fgets(line, 1024, stdin); - if(ptr == NULL ){ + if (ptr == NULL) { printf("can't read input\n"); exit(0); } diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 53c8238..80e20d7 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, +// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -592,39 +593,40 @@ bool dram_t::issue_col_command(int j) { bk[j]->mrq = NULL; } } else - // correct row activated for a WRITE - if (!issued && !CCDc && !bk[j]->RCDWRc && !(bkgrp[grp]->CCDLc) && - (bk[j]->curr_row == bk[j]->mrq->row) && (bk[j]->mrq->rw == WRITE) && - (RTWc == 0) && (bk[j]->state == BANK_ACTIVE) && !rwq->full()) { - if (rw == READ) { - rw = WRITE; - rwq->set_min_length(m_config->WL); - } - rwq->push(bk[j]->mrq); + // correct row activated for a WRITE + if (!issued && !CCDc && !bk[j]->RCDWRc && !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && (bk[j]->mrq->rw == WRITE) && + (RTWc == 0) && (bk[j]->state == BANK_ACTIVE) && !rwq->full()) { + if (rw == READ) { + rw = WRITE; + rwq->set_min_length(m_config->WL); + } + rwq->push(bk[j]->mrq); - bk[j]->mrq->txbytes += m_config->dram_atom_size; - CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; - WTRc = m_config->tWTR; - bk[j]->WTPc = m_config->tWTP; - issued = true; + bk[j]->mrq->txbytes += m_config->dram_atom_size; + CCDc = m_config->tCCD; + bkgrp[grp]->CCDLc = m_config->tCCDL; + WTRc = m_config->tWTR; + bk[j]->WTPc = m_config->tWTP; + issued = true; - if (bk[j]->mrq->data->get_access_type() == L2_WRBK_ACC) - n_wr_WB++; - else - n_wr++; - bwutil += m_config->BL / m_config->data_command_freq_ratio; - bwutil_partial += m_config->BL / m_config->data_command_freq_ratio; + if (bk[j]->mrq->data->get_access_type() == L2_WRBK_ACC) + n_wr_WB++; + else + n_wr++; + bwutil += m_config->BL / m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL / m_config->data_command_freq_ratio; #ifdef DRAM_VERIFY - PRINT_CYCLE = 1; - printf("\tWR Bk:%d Row:%03x Col:%03x \n", j, bk[j]->curr_row, - bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); + PRINT_CYCLE = 1; + printf( + "\tWR Bk:%d Row:%03x Col:%03x \n", j, bk[j]->curr_row, + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); #endif - // transfer done - if (!(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes)) { - bk[j]->mrq = NULL; + // transfer done + if (!(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes)) { + bk[j]->mrq = NULL; + } } - } } return issued; @@ -660,23 +662,23 @@ bool dram_t::issue_row_command(int j) { } else - // different row activated - if ((!issued) && (bk[j]->curr_row != bk[j]->mrq->row) && - (bk[j]->state == BANK_ACTIVE) && - (!bk[j]->RASc && !bk[j]->WTPc && !bk[j]->RTPc && - !bkgrp[grp]->RTPLc)) { - // make the bank idle again - bk[j]->state = BANK_IDLE; - bk[j]->RPc = m_config->tRP; - prio = (j + 1) % m_config->nbk; - issued = true; - n_pre++; - n_pre_partial++; + // different row activated + if ((!issued) && (bk[j]->curr_row != bk[j]->mrq->row) && + (bk[j]->state == BANK_ACTIVE) && + (!bk[j]->RASc && !bk[j]->WTPc && !bk[j]->RTPc && + !bkgrp[grp]->RTPLc)) { + // make the bank idle again + bk[j]->state = BANK_IDLE; + bk[j]->RPc = m_config->tRP; + prio = (j + 1) % m_config->nbk; + issued = true; + n_pre++; + n_pre_partial++; #ifdef DRAM_VERIFY - PRINT_CYCLE = 1; - printf("\tPRE BK:%d Row:%03x \n", j, bk[j]->curr_row); + PRINT_CYCLE = 1; + printf("\tPRE BK:%d Row:%03x \n", j, bk[j]->curr_row); #endif - } + } } return issued; } @@ -880,5 +882,5 @@ unsigned dram_t::get_bankgrp_number(unsigned i) { } else { assert(1); } - return 0; // we should never get here + return 0; // we should never get here } diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 90ea3e4..9e9517b 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Ivan Sham, Ali Bakhoda, // George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index f4448d3..32cc56b 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1,18 +1,19 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, // Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, // Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -287,10 +288,11 @@ enum cache_request_status tag_array::probe(new_addr_type addr, unsigned &idx, // number of dirty lines / total lines in the cache float dirty_line_percentage = ((float)m_dirty / (m_config.m_nset * m_config.m_assoc)) * 100; - // If the cacheline is from a load op (not modified), + // If the cacheline is from a load op (not modified), // or the total dirty cacheline is above a specific value, - // Then this cacheline is eligible to be considered for replacement candidate - // i.e. Only evict clean cachelines until total dirty cachelines reach the limit. + // Then this cacheline is eligible to be considered for replacement + // candidate i.e. Only evict clean cachelines until total dirty cachelines + // reach the limit. if (!line->is_modified_line() || dirty_line_percentage >= m_config.m_wr_percent) { all_reserved = false; @@ -411,7 +413,7 @@ void tag_array::fill(new_addr_type addr, unsigned time, enum cache_request_status status = probe(addr, idx, mask, is_write); if (status == RESERVATION_FAIL) { - return; + return; } bool before = m_lines[idx]->is_modified_line(); @@ -437,7 +439,8 @@ void tag_array::fill(new_addr_type addr, unsigned time, void tag_array::fill(unsigned index, unsigned time, mem_fetch *mf) { assert(m_config.m_alloc_policy == ON_MISS); bool before = m_lines[index]->is_modified_line(); - m_lines[index]->fill(time, mf->get_access_sector_mask(), mf->get_access_byte_mask()); + m_lines[index]->fill(time, mf->get_access_sector_mask(), + mf->get_access_byte_mask()); if (m_lines[index]->is_modified_line() && !before) { m_dirty++; } @@ -1210,15 +1213,14 @@ void data_cache::update_m_readable(mem_fetch *mf, unsigned cache_index) { if (mf->get_access_sector_mask().test(i)) { bool all_set = true; for (unsigned k = i * SECTOR_SIZE; k < (i + 1) * SECTOR_SIZE; k++) { - // If any bit in the byte mask (within the sector) is not set, + // If any bit in the byte mask (within the sector) is not set, // the sector is unreadble if (!block->get_dirty_byte_mask().test(k)) { all_set = false; break; } } - if (all_set) - block->set_m_readable(true, mf->get_access_sector_mask()); + if (all_set) block->set_m_readable(true, mf->get_access_sector_mask()); } } } @@ -1239,7 +1241,7 @@ cache_request_status data_cache::wr_hit_wb(new_addr_type addr, } block->set_status(MODIFIED, mf->get_access_sector_mask()); block->set_byte_mask(mf); - update_m_readable(mf,cache_index); + update_m_readable(mf, cache_index); return HIT; } @@ -1263,7 +1265,7 @@ cache_request_status data_cache::wr_hit_wt(new_addr_type addr, } block->set_status(MODIFIED, mf->get_access_sector_mask()); block->set_byte_mask(mf); - update_m_readable(mf,cache_index); + update_m_readable(mf, cache_index); // generate a write-through send_write_request(mf, cache_event(WRITE_REQUEST_SENT), time, events); @@ -1559,7 +1561,7 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( if (m_status == HIT_RESERVED) block->set_readable_on_fill(true, mf->get_access_sector_mask()); } - update_m_readable(mf,cache_index); + update_m_readable(mf, cache_index); if (m_status != RESERVATION_FAIL) { // If evicted block is modified and not a write-through diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index ad41320..5fd40a9 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University +// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, +// Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, Timothy G. Rogers The +// University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -499,7 +500,7 @@ struct sector_cache_block : public cache_block_t { for (unsigned i = 0; i < SECTOR_CHUNCK_SIZE; ++i) { if (sector_mask.to_ulong() & (1 << i)) return i; } - return SECTOR_CHUNCK_SIZE; //error + return SECTOR_CHUNCK_SIZE; // error } }; @@ -564,12 +565,10 @@ class cache_config { char ct, rp, wp, ap, mshr_type, wap, sif; int ntok = - sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", - &ct, &m_nset, &m_line_sz, &m_assoc, - &rp, &wp, &ap, &wap, &sif, - &mshr_type, &m_mshr_entries, &m_mshr_max_merge, - &m_miss_queue_size, &m_result_fifo_entries, - &m_data_port_width); + sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", &ct, + &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap, &sif, + &mshr_type, &m_mshr_entries, &m_mshr_max_merge, + &m_miss_queue_size, &m_result_fifo_entries, &m_data_port_width); if (ntok < 12) { if (!strcmp(config, "none")) { @@ -726,15 +725,14 @@ class cache_config { } if (m_cache_type == SECTOR) { - bool cond = - m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE && - m_line_sz % SECTOR_SIZE == 0; - if(!cond){ - std::cerr<<"error: For sector cache, the simulator uses hard-coded " - "SECTOR_SIZE and SECTOR_CHUNCK_SIZE. The line size " - "must be product of both values.\n"; - assert(0); - } + bool cond = m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE && + m_line_sz % SECTOR_SIZE == 0; + if (!cond) { + std::cerr << "error: For sector cache, the simulator uses hard-coded " + "SECTOR_SIZE and SECTOR_CHUNCK_SIZE. The line size " + "must be product of both values.\n"; + assert(0); + } } // default: port to data array width and granularity = line size diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 47c0b4a..1cb8a25 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, George L. Yuan, -// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas, +// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -80,7 +81,7 @@ class gpgpu_sim_wrapper {}; #include <sstream> #include <string> -// #define MAX(a, b) (((a) > (b)) ? (a) : (b)) //redefined +// #define MAX(a, b) (((a) > (b)) ? (a) : (b)) //redefined bool g_interactive_debugger_enabled = false; @@ -97,7 +98,6 @@ tr1_hash_map<new_addr_type, unsigned> address_random_interleaving; #include "mem_latency_stat.h" - void power_config::reg_options(class OptionParser *opp) { option_parser_register(opp, "-accelwattch_xml_file", OPT_CSTR, &g_power_config_name, "AccelWattch XML file", @@ -111,91 +111,106 @@ void power_config::reg_options(class OptionParser *opp) { &g_power_per_cycle_dump, "Dump detailed power output each cycle", "0"); - - - option_parser_register(opp, "-hw_perf_file_name", OPT_CSTR, - &g_hw_perf_file_name, "Hardware Performance Statistics file", - "hw_perf.csv"); + &g_hw_perf_file_name, + "Hardware Performance Statistics file", "hw_perf.csv"); - option_parser_register(opp, "-hw_perf_bench_name", OPT_CSTR, - &g_hw_perf_bench_name, "Kernel Name in Hardware Performance Statistics file", - ""); + option_parser_register( + opp, "-hw_perf_bench_name", OPT_CSTR, &g_hw_perf_bench_name, + "Kernel Name in Hardware Performance Statistics file", ""); option_parser_register(opp, "-power_simulation_mode", OPT_INT32, &g_power_simulation_mode, - "Switch performance counter input for power simulation (0=Sim, 1=HW, 2=HW-Sim Hybrid)", "0"); + "Switch performance counter input for power " + "simulation (0=Sim, 1=HW, 2=HW-Sim Hybrid)", + "0"); - option_parser_register(opp, "-dvfs_enabled", OPT_BOOL, - &g_dvfs_enabled, + option_parser_register(opp, "-dvfs_enabled", OPT_BOOL, &g_dvfs_enabled, "Turn on DVFS for power model", "0"); option_parser_register(opp, "-aggregate_power_stats", OPT_BOOL, &g_aggregate_power_stats, "Accumulate power across all kernels", "0"); - //Accelwattch Hyrbid Configuration + // Accelwattch Hyrbid Configuration - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L1_RH", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L1_RH], - "Get L1 Read Hits for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L1_RM", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L1_RM], - "Get L1 Read Misses for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L1_WH", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L1_WH], - "Get L1 Write Hits for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L1_WM", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L1_WM], - "Get L1 Write Misses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L1_RH", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L1_RH], + "Get L1 Read Hits for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L1_RM", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L1_RM], + "Get L1 Read Misses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L1_WH", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L1_WH], + "Get L1 Write Hits for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L1_WM", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L1_WM], + "Get L1 Write Misses for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L2_RH", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L2_RH], - "Get L2 Read Hits for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L2_RM", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L2_RM], - "Get L2 Read Misses for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L2_WH", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L2_WH], - "Get L2 Write Hits for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_L2_WM", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_L2_WM], - "Get L2 Write Misses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L2_RH", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L2_RH], + "Get L2 Read Hits for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L2_RM", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L2_RM], + "Get L2 Read Misses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L2_WH", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L2_WH], + "Get L2 Write Hits for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_L2_WM", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_L2_WM], + "Get L2 Write Misses for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_CC_ACC", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_CC_ACC], - "Get Constant Cache Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_CC_ACC", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_CC_ACC], + "Get Constant Cache Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_SHARED_ACC", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_SHRD_ACC], - "Get Shared Memory Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_SHARED_ACC", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_SHRD_ACC], + "Get Shared Memory Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); option_parser_register(opp, "-accelwattch_hybrid_perfsim_DRAM_RD", OPT_BOOL, &accelwattch_hybrid_configuration[HW_DRAM_RD], - "Get DRAM Reads for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_DRAM_WR", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_DRAM_WR], - "Get DRAM Writes for Accelwattch-Hybrid from Accel-Sim", "0"); - - option_parser_register(opp, "-accelwattch_hybrid_perfsim_NOC", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_NOC], - "Get Interconnect Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); + "Get DRAM Reads for Accelwattch-Hybrid from Accel-Sim", + "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_DRAM_WR", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_DRAM_WR], + "Get DRAM Writes for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_PIPE_DUTY", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_PIPE_DUTY], - "Get Pipeline Duty Cycle Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_NOC", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_NOC], + "Get Interconnect Acesses for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_NUM_SM_IDLE", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_NUM_SM_IDLE], - "Get Number of Idle SMs for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_PIPE_DUTY", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_PIPE_DUTY], + "Get Pipeline Duty Cycle Acesses for Accelwattch-Hybrid from Accel-Sim", + "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_CYCLES", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_CYCLES], - "Get Executed Cycles for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_NUM_SM_IDLE", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_NUM_SM_IDLE], + "Get Number of Idle SMs for Accelwattch-Hybrid from Accel-Sim", "0"); - option_parser_register(opp, "-accelwattch_hybrid_perfsim_VOLTAGE", OPT_BOOL, - &accelwattch_hybrid_configuration[HW_VOLTAGE], - "Get Chip Voltage for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_CYCLES", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_CYCLES], + "Get Executed Cycles for Accelwattch-Hybrid from Accel-Sim", "0"); + option_parser_register( + opp, "-accelwattch_hybrid_perfsim_VOLTAGE", OPT_BOOL, + &accelwattch_hybrid_configuration[HW_VOLTAGE], + "Get Chip Voltage for Accelwattch-Hybrid from Accel-Sim", "0"); // Output Data Formats option_parser_register( @@ -702,7 +717,8 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) { option_parser_register( opp, "-gpgpu_max_concurrent_kernel", OPT_INT32, &max_concurrent_kernel, "maximum kernels that can run concurrently on GPU, set this value " - "according to max resident grids for your compute capability", "32"); + "according to max resident grids for your compute capability", + "32"); option_parser_register( opp, "-gpgpu_cflog_interval", OPT_INT32, &gpgpu_cflog_interval, "Interval between each snapshot in control flow logger", "0"); @@ -924,8 +940,9 @@ gpgpu_sim::gpgpu_sim(const gpgpu_sim_config &config, gpgpu_context *ctx) ptx_file_line_stats_create_exposed_latency_tracker(m_config.num_shader()); #ifdef GPGPUSIM_POWER_MODEL - m_gpgpusim_wrapper = new gpgpu_sim_wrapper(config.g_power_simulation_enabled, - config.g_power_config_name, config.g_power_simulation_mode, config.g_dvfs_enabled); + m_gpgpusim_wrapper = new gpgpu_sim_wrapper( + config.g_power_simulation_enabled, config.g_power_config_name, + config.g_power_simulation_mode, config.g_dvfs_enabled); #endif m_shader_stats = new shader_core_stats(m_shader_config); @@ -1157,8 +1174,7 @@ void gpgpu_sim::update_stats() { gpu_occupancy = occupancy_stats(); } -PowerscalingCoefficients *gpgpu_sim::get_scaling_coeffs() -{ +PowerscalingCoefficients *gpgpu_sim::get_scaling_coeffs() { return m_gpgpusim_wrapper->get_scaling_coeffs(); } @@ -1243,10 +1259,10 @@ std::string gpgpu_sim::executed_kernel_info_string() { } std::string gpgpu_sim::executed_kernel_name() { - std::stringstream statout; - if( m_executed_kernel_names.size() == 1) - statout << m_executed_kernel_names[0]; - else{ + std::stringstream statout; + if (m_executed_kernel_names.size() == 1) + statout << m_executed_kernel_names[0]; + else { for (unsigned int k = 0; k < m_executed_kernel_names.size(); k++) { statout << m_executed_kernel_names[k] << " "; } @@ -1433,20 +1449,23 @@ void gpgpu_sim::gpu_print_stat() { m_shader_stats->print(stdout); #ifdef GPGPUSIM_POWER_MODEL if (m_config.g_power_simulation_enabled) { - if(m_config.g_power_simulation_mode > 0){ - //if(!m_config.g_aggregate_power_stats) - mcpat_reset_perf_count(m_gpgpusim_wrapper); - calculate_hw_mcpat(m_config, getShaderCoreConfig(), m_gpgpusim_wrapper, - m_power_stats, m_config.gpu_stat_sample_freq, - gpu_tot_sim_cycle, gpu_sim_cycle, gpu_tot_sim_insn, - gpu_sim_insn, m_config.g_power_simulation_mode, m_config.g_dvfs_enabled, - m_config.g_hw_perf_file_name, m_config.g_hw_perf_bench_name, executed_kernel_name(), m_config.accelwattch_hybrid_configuration, m_config.g_aggregate_power_stats); + if (m_config.g_power_simulation_mode > 0) { + // if(!m_config.g_aggregate_power_stats) + mcpat_reset_perf_count(m_gpgpusim_wrapper); + calculate_hw_mcpat(m_config, getShaderCoreConfig(), m_gpgpusim_wrapper, + m_power_stats, m_config.gpu_stat_sample_freq, + gpu_tot_sim_cycle, gpu_sim_cycle, gpu_tot_sim_insn, + gpu_sim_insn, m_config.g_power_simulation_mode, + m_config.g_dvfs_enabled, m_config.g_hw_perf_file_name, + m_config.g_hw_perf_bench_name, executed_kernel_name(), + m_config.accelwattch_hybrid_configuration, + m_config.g_aggregate_power_stats); } m_gpgpusim_wrapper->print_power_kernel_stats( gpu_sim_cycle, gpu_tot_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, kernel_info_str, true); - //if(!m_config.g_aggregate_power_stats) - mcpat_reset_perf_count(m_gpgpusim_wrapper); + // if(!m_config.g_aggregate_power_stats) + mcpat_reset_perf_count(m_gpgpusim_wrapper); } #endif @@ -1810,7 +1829,8 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { "GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, " "initialized @(%lld,%lld), kernel_uid:%u, kernel_name:%s\n", free_cta_hw_id, start_thread, end_thread, m_gpu->gpu_sim_cycle, - m_gpu->gpu_tot_sim_cycle, kernel.get_uid(), kernel.get_name().c_str()); + m_gpu->gpu_tot_sim_cycle, kernel.get_uid(), + kernel.get_name().c_str()); } /////////////////////////////////////////////////////////////////////////////////////////// @@ -1987,11 +2007,11 @@ void gpgpu_sim::cycle() { // McPAT main cycle (interface with McPAT) #ifdef GPGPUSIM_POWER_MODEL if (m_config.g_power_simulation_enabled) { - if(m_config.g_power_simulation_mode == 0){ - mcpat_cycle(m_config, getShaderCoreConfig(), m_gpgpusim_wrapper, - m_power_stats, m_config.gpu_stat_sample_freq, - gpu_tot_sim_cycle, gpu_sim_cycle, gpu_tot_sim_insn, - gpu_sim_insn, m_config.g_dvfs_enabled); + if (m_config.g_power_simulation_mode == 0) { + mcpat_cycle(m_config, getShaderCoreConfig(), m_gpgpusim_wrapper, + m_power_stats, m_config.gpu_stat_sample_freq, + gpu_tot_sim_cycle, gpu_sim_cycle, gpu_tot_sim_insn, + gpu_sim_insn, m_config.g_dvfs_enabled); } } #endif diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index de69ef8..a24ffd3 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University +// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Vijay Kandiah, +// Nikos Hardavellas Mahmoud Khairy, Junrui Pan, Timothy G. Rogers The +// University of British Columbia, Northwestern University, Purdue University // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -28,7 +29,6 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. - #ifndef GPU_SIM_H #define GPU_SIM_H @@ -72,7 +72,7 @@ extern tr1_hash_map<new_addr_type, unsigned> address_random_interleaving; enum dram_ctrl_t { DRAM_FIFO = 0, DRAM_FRFCFS = 1 }; enum hw_perf_t { - HW_BENCH_NAME=0, + HW_BENCH_NAME = 0, HW_KERNEL_NAME, HW_L1_RH, HW_L1_RM, @@ -108,7 +108,7 @@ struct power_config { s++; } char buf1[1024]; - //snprintf(buf1, 1024, "accelwattch_power_report__%s.log", date); + // snprintf(buf1, 1024, "accelwattch_power_report__%s.log", date); snprintf(buf1, 1024, "accelwattch_power_report.log"); g_power_filename = strdup(buf1); char buf2[1024]; @@ -155,7 +155,6 @@ struct power_config { double gpu_steady_power_deviation; double gpu_steady_min_period; - char *g_hw_perf_file_name; char *g_hw_perf_bench_name; int g_power_simulation_mode; diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 5b63765..8469453 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, +// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -390,7 +391,8 @@ void memory_partition_unit::set_done(mem_fetch *mf) { void memory_partition_unit::set_dram_power_stats( unsigned &n_cmd, unsigned &n_activity, unsigned &n_nop, unsigned &n_act, - unsigned &n_pre, unsigned &n_rd, unsigned &n_wr, unsigned &n_wr_WB, unsigned &n_req) const { + unsigned &n_pre, unsigned &n_rd, unsigned &n_wr, unsigned &n_wr_WB, + unsigned &n_req) const { m_dram->set_dram_power_stats(n_cmd, n_activity, n_nop, n_act, n_pre, n_rd, n_wr, n_wr_WB, n_req); } diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 7fa1f29..ccf9b70 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -1,17 +1,18 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc index fe7bc74..7e1ab5b 100644 --- a/src/gpgpu-sim/local_interconnect.cc +++ b/src/gpgpu-sim/local_interconnect.cc @@ -148,7 +148,7 @@ void xbar_router::RR_Advance() { } } } - next_node_id = next_node_id + 1 ; + next_node_id = next_node_id + 1; next_node_id = (next_node_id % total_nodes); conflicts += conflict_sub; diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc index 45a09bc..cddb6e9 100644 --- a/src/gpgpu-sim/power_interface.cc +++ b/src/gpgpu-sim/power_interface.cc @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler +// Hetherington, Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, +// Timothy G. Rogers The University of British Columbia, Northwestern +// University, Purdue University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -28,10 +29,8 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. - #include "power_interface.h" - void init_mcpat(const gpgpu_sim_config &config, class gpgpu_sim_wrapper *wrapper, unsigned stat_sample_freq, unsigned tot_inst, unsigned inst) { @@ -42,11 +41,9 @@ void init_mcpat(const gpgpu_sim_config &config, config.g_power_simulation_enabled, config.g_power_trace_enabled, config.g_steady_power_levels_enabled, config.g_power_per_cycle_dump, config.gpu_steady_power_deviation, config.gpu_steady_min_period, - config.g_power_trace_zlevel, tot_inst + inst, stat_sample_freq, - config.g_power_simulation_mode, - config.g_dvfs_enabled, - config.get_core_freq()/1000000, - config.num_shader()); + config.g_power_trace_zlevel, tot_inst + inst, stat_sample_freq, + config.g_power_simulation_mode, config.g_dvfs_enabled, + config.get_core_freq() / 1000000, config.num_shader()); } void mcpat_cycle(const gpgpu_sim_config &config, @@ -63,8 +60,9 @@ void mcpat_cycle(const gpgpu_sim_config &config, } if ((tot_cycle + cycle) % stat_sample_freq == 0) { - if(dvfs_enabled){ - wrapper->set_model_voltage(1); //performance model needs to support this. + if (dvfs_enabled) { + wrapper->set_model_voltage(1); // performance model needs to support + // this. } wrapper->set_inst_power( @@ -85,14 +83,17 @@ void mcpat_cycle(const gpgpu_sim_config &config, power_stats->get_inst_c_misses(0)); // Constant Cache, shared memory, texture cache - wrapper->set_ccache_power(power_stats->get_const_accessess(0), 0); //assuming all HITS in constant cache for now + wrapper->set_ccache_power( + power_stats->get_const_accessess(0), + 0); // assuming all HITS in constant cache for now wrapper->set_tcache_power(power_stats->get_texture_c_hits(), power_stats->get_texture_c_misses()); wrapper->set_shrd_mem_power(power_stats->get_shmem_access(0)); - wrapper->set_l1cache_power( - power_stats->get_l1d_read_hits(0), power_stats->get_l1d_read_misses(0), - power_stats->get_l1d_write_hits(0), power_stats->get_l1d_write_misses(0)); + wrapper->set_l1cache_power(power_stats->get_l1d_read_hits(0), + power_stats->get_l1d_read_misses(0), + power_stats->get_l1d_write_hits(0), + power_stats->get_l1d_write_misses(0)); wrapper->set_l2cache_power( power_stats->get_l2_read_hits(0), power_stats->get_l2_read_misses(0), @@ -120,24 +121,23 @@ void mcpat_cycle(const gpgpu_sim_config &config, // Execution pipeline accesses // FPU (SP) accesses, Integer ALU (not present in Tesla), Sfu accesses - wrapper->set_int_accesses(power_stats->get_ialu_accessess(0), - power_stats->get_intmul24_accessess(0), - power_stats->get_intmul32_accessess(0), - power_stats->get_intmul_accessess(0), + wrapper->set_int_accesses(power_stats->get_ialu_accessess(0), + power_stats->get_intmul24_accessess(0), + power_stats->get_intmul32_accessess(0), + power_stats->get_intmul_accessess(0), power_stats->get_intdiv_accessess(0)); - wrapper->set_dp_accesses(power_stats->get_dp_accessess(0), - power_stats->get_dpmul_accessess(0), - power_stats->get_dpdiv_accessess(0)); + wrapper->set_dp_accesses(power_stats->get_dp_accessess(0), + power_stats->get_dpmul_accessess(0), + power_stats->get_dpdiv_accessess(0)); - wrapper->set_fp_accesses(power_stats->get_fp_accessess(0), - power_stats->get_fpmul_accessess(0), - power_stats->get_fpdiv_accessess(0)); + wrapper->set_fp_accesses(power_stats->get_fp_accessess(0), + power_stats->get_fpmul_accessess(0), + power_stats->get_fpdiv_accessess(0)); - wrapper->set_trans_accesses(power_stats->get_sqrt_accessess(0), - power_stats->get_log_accessess(0), - power_stats->get_sin_accessess(0), - power_stats->get_exp_accessess(0)); + wrapper->set_trans_accesses( + power_stats->get_sqrt_accessess(0), power_stats->get_log_accessess(0), + power_stats->get_sin_accessess(0), power_stats->get_exp_accessess(0)); wrapper->set_tensor_accesses(power_stats->get_tensor_accessess(0)); @@ -154,23 +154,21 @@ void mcpat_cycle(const gpgpu_sim_config &config, (power_stats->get_sp_active_lanes()) / stat_sample_freq; float avg_sfu_active_lanes = (power_stats->get_sfu_active_lanes()) / stat_sample_freq; - if(avg_sp_active_lanes >32.0 ) - avg_sp_active_lanes = 32.0; - if(avg_sfu_active_lanes >32.0 ) - avg_sfu_active_lanes = 32.0; + if (avg_sp_active_lanes > 32.0) avg_sp_active_lanes = 32.0; + if (avg_sfu_active_lanes > 32.0) avg_sfu_active_lanes = 32.0; assert(avg_sp_active_lanes <= 32); assert(avg_sfu_active_lanes <= 32); wrapper->set_active_lanes_power(avg_sp_active_lanes, avg_sfu_active_lanes); - double n_icnt_simt_to_mem = - (double) - power_stats->get_icnt_simt_to_mem(0); // # flits from SIMT clusters - // to memory partitions - double n_icnt_mem_to_simt = - (double) - power_stats->get_icnt_mem_to_simt(0); // # flits from memory - // partitions to SIMT clusters - wrapper->set_NoC_power(n_icnt_mem_to_simt + n_icnt_simt_to_mem); // Number of flits traversing the interconnect + double n_icnt_simt_to_mem = (double)power_stats->get_icnt_simt_to_mem( + 0); // # flits from SIMT clusters + // to memory partitions + double n_icnt_mem_to_simt = (double)power_stats->get_icnt_mem_to_simt( + 0); // # flits from memory + // partitions to SIMT clusters + wrapper->set_NoC_power( + n_icnt_mem_to_simt + + n_icnt_simt_to_mem); // Number of flits traversing the interconnect wrapper->compute(); @@ -191,68 +189,77 @@ void mcpat_reset_perf_count(class gpgpu_sim_wrapper *wrapper) { wrapper->reset_counters(); } -bool parse_hw_file(char* hwpowerfile, bool find_target_kernel, vector<string> &hw_data, char* benchname, std::string executed_kernelname){ +bool parse_hw_file(char *hwpowerfile, bool find_target_kernel, + vector<string> &hw_data, char *benchname, + std::string executed_kernelname) { fstream hw_file; hw_file.open(hwpowerfile, ios::in); string line, word, temp; - while(!hw_file.eof()){ + while (!hw_file.eof()) { hw_data.clear(); getline(hw_file, line); stringstream s(line); - while (getline(s,word,',')){ + while (getline(s, word, ',')) { hw_data.push_back(word); } - if(hw_data[HW_BENCH_NAME] == std::string(benchname)){ - if(find_target_kernel){ - if(hw_data[HW_KERNEL_NAME] == ""){ + if (hw_data[HW_BENCH_NAME] == std::string(benchname)) { + if (find_target_kernel) { + if (hw_data[HW_KERNEL_NAME] == "") { hw_file.close(); return true; - } - else{ - if(hw_data[HW_KERNEL_NAME] == executed_kernelname){ + } else { + if (hw_data[HW_KERNEL_NAME] == executed_kernelname) { hw_file.close(); return true; } } - } - else{ + } else { hw_file.close(); return true; } - } + } } hw_file.close(); return false; } - -void calculate_hw_mcpat(const gpgpu_sim_config &config, - const shader_core_config *shdr_config, - class gpgpu_sim_wrapper *wrapper, - class power_stat_t *power_stats, unsigned stat_sample_freq, - unsigned tot_cycle, unsigned cycle, unsigned tot_inst, - unsigned inst, int power_simulation_mode, bool dvfs_enabled, char* hwpowerfile, - char* benchname, std::string executed_kernelname, - const bool *accelwattch_hybrid_configuration, bool aggregate_power_stats){ - +void calculate_hw_mcpat( + const gpgpu_sim_config &config, const shader_core_config *shdr_config, + class gpgpu_sim_wrapper *wrapper, class power_stat_t *power_stats, + unsigned stat_sample_freq, unsigned tot_cycle, unsigned cycle, + unsigned tot_inst, unsigned inst, int power_simulation_mode, + bool dvfs_enabled, char *hwpowerfile, char *benchname, + std::string executed_kernelname, + const bool *accelwattch_hybrid_configuration, bool aggregate_power_stats) { /* Reading HW data from CSV file */ vector<string> hw_data; bool kernel_found = false; - kernel_found = parse_hw_file(hwpowerfile, true, hw_data, benchname, executed_kernelname); //Searching for matching executed_kernelname. - if(!kernel_found) - kernel_found = parse_hw_file(hwpowerfile, false, hw_data, benchname, executed_kernelname); //Searching for any kernel with same benchname. - assert("Could not find perf stats for the target benchmark in hwpowerfile.\n" && (kernel_found)); - unsigned perf_cycles = static_cast<unsigned int>(std::stod(hw_data[HW_CYCLES]) + 0.5); - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_CYCLES])) + kernel_found = parse_hw_file( + hwpowerfile, true, hw_data, benchname, + executed_kernelname); // Searching for matching executed_kernelname. + if (!kernel_found) + kernel_found = parse_hw_file( + hwpowerfile, false, hw_data, benchname, + executed_kernelname); // Searching for any kernel with same benchname. + assert( + "Could not find perf stats for the target benchmark in hwpowerfile.\n" && + (kernel_found)); + unsigned perf_cycles = + static_cast<unsigned int>(std::stod(hw_data[HW_CYCLES]) + 0.5); + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_CYCLES])) perf_cycles = cycle; - wrapper->init_mcpat_hw_mode(perf_cycles); //total PERF MODEL cycles for current kernel + wrapper->init_mcpat_hw_mode( + perf_cycles); // total PERF MODEL cycles for current kernel - if(dvfs_enabled){ - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_VOLTAGE])) - wrapper->set_model_voltage(1); //performance model needs to support this - else - wrapper->set_model_voltage(std::stod(hw_data[HW_VOLTAGE])); //performance model needs to support this + if (dvfs_enabled) { + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_VOLTAGE])) + wrapper->set_model_voltage(1); // performance model needs to support this + else + wrapper->set_model_voltage(std::stod( + hw_data[HW_VOLTAGE])); // performance model needs to support this } double l1_read_hits = std::stod(hw_data[HW_L1_RH]); @@ -260,266 +267,302 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config, double l1_write_hits = std::stod(hw_data[HW_L1_WH]); double l1_write_misses = std::stod(hw_data[HW_L1_WM]); - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_RH])) - l1_read_hits = power_stats->get_l1d_read_hits(1) - power_stats->l1r_hits_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_RM])) - l1_read_misses = power_stats->get_l1d_read_misses(1) - power_stats->l1r_misses_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_WH])) - l1_write_hits = power_stats->get_l1d_write_hits(1) - power_stats->l1w_hits_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_WM])) - l1_write_misses = power_stats->get_l1d_write_misses(1) - power_stats->l1w_misses_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L1_RH])) + l1_read_hits = + power_stats->get_l1d_read_hits(1) - power_stats->l1r_hits_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L1_RM])) + l1_read_misses = + power_stats->get_l1d_read_misses(1) - power_stats->l1r_misses_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L1_WH])) + l1_write_hits = + power_stats->get_l1d_write_hits(1) - power_stats->l1w_hits_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L1_WM])) + l1_write_misses = + power_stats->get_l1d_write_misses(1) - power_stats->l1w_misses_kernel; - if(aggregate_power_stats){ - power_stats->tot_inst_execution += power_stats->get_total_inst(1); - power_stats->tot_int_inst_execution += power_stats->get_total_int_inst(1); - power_stats->tot_fp_inst_execution += power_stats->get_total_fp_inst(1); - power_stats->commited_inst_execution += power_stats->get_committed_inst(1); - wrapper->set_inst_power( - shdr_config->gpgpu_clock_gated_lanes, cycle, //TODO: core.[0] cycles counts don't matter, remove this + if (aggregate_power_stats) { + power_stats->tot_inst_execution += power_stats->get_total_inst(1); + power_stats->tot_int_inst_execution += power_stats->get_total_int_inst(1); + power_stats->tot_fp_inst_execution += power_stats->get_total_fp_inst(1); + power_stats->commited_inst_execution += power_stats->get_committed_inst(1); + wrapper->set_inst_power( + shdr_config->gpgpu_clock_gated_lanes, + cycle, // TODO: core.[0] cycles counts don't matter, remove this cycle, power_stats->tot_inst_execution, power_stats->tot_int_inst_execution, power_stats->tot_fp_inst_execution, - l1_read_hits + l1_read_misses, - l1_write_hits + l1_write_misses, + l1_read_hits + l1_read_misses, l1_write_hits + l1_write_misses, power_stats->commited_inst_execution); - } - else{ - wrapper->set_inst_power( - shdr_config->gpgpu_clock_gated_lanes, cycle, //TODO: core.[0] cycles counts don't matter, remove this + } else { + wrapper->set_inst_power( + shdr_config->gpgpu_clock_gated_lanes, + cycle, // TODO: core.[0] cycles counts don't matter, remove this cycle, power_stats->get_total_inst(1), power_stats->get_total_int_inst(1), power_stats->get_total_fp_inst(1), - l1_read_hits + l1_read_misses, - l1_write_hits + l1_write_misses, + l1_read_hits + l1_read_misses, l1_write_hits + l1_write_misses, power_stats->get_committed_inst(1)); } - // Single RF for both int and fp ops -- activity factor set to 0 for Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for register files - wrapper->set_regfile_power(power_stats->get_regfile_reads(1), - power_stats->get_regfile_writes(1), - power_stats->get_non_regfile_operands(1)); + // Single RF for both int and fp ops -- activity factor set to 0 for + // Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for register + // files + wrapper->set_regfile_power(power_stats->get_regfile_reads(1), + power_stats->get_regfile_writes(1), + power_stats->get_non_regfile_operands(1)); - // Instruction cache stats -- activity factor set to 0 for Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for instruction cache - wrapper->set_icache_power(power_stats->get_inst_c_hits(1) - power_stats->l1i_hits_kernel, - power_stats->get_inst_c_misses(1) - power_stats->l1i_misses_kernel); + // Instruction cache stats -- activity factor set to 0 for Accelwattch HW and + // Accelwattch Hybrid because no HW Perf Stats for instruction cache + wrapper->set_icache_power( + power_stats->get_inst_c_hits(1) - power_stats->l1i_hits_kernel, + power_stats->get_inst_c_misses(1) - power_stats->l1i_misses_kernel); - // Constant Cache, shared memory, texture cache - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_CC_ACC])) - wrapper->set_ccache_power(power_stats->get_const_accessess(1) - power_stats->cc_accesses_kernel, 0); //assuming all HITS in constant cache for now - else - wrapper->set_ccache_power(std::stod(hw_data[HW_CC_ACC]), 0); //assuming all HITS in constant cache for now + // Constant Cache, shared memory, texture cache + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_CC_ACC])) + wrapper->set_ccache_power( + power_stats->get_const_accessess(1) - power_stats->cc_accesses_kernel, + 0); // assuming all HITS in constant cache for now + else + wrapper->set_ccache_power( + std::stod(hw_data[HW_CC_ACC]), + 0); // assuming all HITS in constant cache for now - - // wrapper->set_tcache_power(power_stats->get_texture_c_hits(), - // power_stats->get_texture_c_misses()); + // wrapper->set_tcache_power(power_stats->get_texture_c_hits(), + // power_stats->get_texture_c_misses()); - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_SHRD_ACC])) - wrapper->set_shrd_mem_power(power_stats->get_shmem_access(1) - power_stats->shared_accesses_kernel); - else - wrapper->set_shrd_mem_power(std::stod(hw_data[HW_SHRD_ACC])); + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_SHRD_ACC])) + wrapper->set_shrd_mem_power(power_stats->get_shmem_access(1) - + power_stats->shared_accesses_kernel); + else + wrapper->set_shrd_mem_power(std::stod(hw_data[HW_SHRD_ACC])); - wrapper->set_l1cache_power( l1_read_hits, l1_read_misses, l1_write_hits, l1_write_misses); + wrapper->set_l1cache_power(l1_read_hits, l1_read_misses, l1_write_hits, + l1_write_misses); - double l2_read_hits = std::stod(hw_data[HW_L2_RH]); - double l2_read_misses = std::stod(hw_data[HW_L2_RM]); - double l2_write_hits = std::stod(hw_data[HW_L2_WH]); - double l2_write_misses = std::stod(hw_data[HW_L2_WM]); + double l2_read_hits = std::stod(hw_data[HW_L2_RH]); + double l2_read_misses = std::stod(hw_data[HW_L2_RM]); + double l2_write_hits = std::stod(hw_data[HW_L2_WH]); + double l2_write_misses = std::stod(hw_data[HW_L2_WM]); - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L2_RH])) - l2_read_hits = power_stats->get_l2_read_hits(1) - power_stats->l2r_hits_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L2_RM])) - l2_read_misses = power_stats->get_l2_read_misses(1) - power_stats->l2r_misses_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L2_WH])) - l2_write_hits = power_stats->get_l2_write_hits(1) - power_stats->l2w_hits_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L2_WM])) - l2_write_misses = power_stats->get_l2_write_misses(1) - power_stats->l2w_misses_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L2_RH])) + l2_read_hits = + power_stats->get_l2_read_hits(1) - power_stats->l2r_hits_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L2_RM])) + l2_read_misses = + power_stats->get_l2_read_misses(1) - power_stats->l2r_misses_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L2_WH])) + l2_write_hits = + power_stats->get_l2_write_hits(1) - power_stats->l2w_hits_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_L2_WM])) + l2_write_misses = + power_stats->get_l2_write_misses(1) - power_stats->l2w_misses_kernel; - wrapper->set_l2cache_power(l2_read_hits, l2_read_misses, l2_write_hits, l2_write_misses); - - float active_sms = (*power_stats->m_active_sms) / stat_sample_freq; - float num_cores = shdr_config->num_shader(); - float num_idle_core = num_cores - active_sms; - wrapper->set_num_cores(num_cores); - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_NUM_SM_IDLE])) - wrapper->set_idle_core_power(num_idle_core); - else - wrapper->set_idle_core_power(std::stod(hw_data[HW_NUM_SM_IDLE])); + wrapper->set_l2cache_power(l2_read_hits, l2_read_misses, l2_write_hits, + l2_write_misses); - float pipeline_duty_cycle = - ((*power_stats->m_average_pipeline_duty_cycle / (stat_sample_freq)) < - 0.8) - ? ((*power_stats->m_average_pipeline_duty_cycle) / stat_sample_freq) - : 0.8; - - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_PIPE_DUTY])) - wrapper->set_duty_cycle_power(pipeline_duty_cycle); - else - wrapper->set_duty_cycle_power(std::stod(hw_data[HW_PIPE_DUTY])); + float active_sms = (*power_stats->m_active_sms) / stat_sample_freq; + float num_cores = shdr_config->num_shader(); + float num_idle_core = num_cores - active_sms; + wrapper->set_num_cores(num_cores); + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_NUM_SM_IDLE])) + wrapper->set_idle_core_power(num_idle_core); + else + wrapper->set_idle_core_power(std::stod(hw_data[HW_NUM_SM_IDLE])); - // Memory Controller - - double dram_reads = std::stod(hw_data[HW_DRAM_RD]); - double dram_writes = std::stod(hw_data[HW_DRAM_WR]); - double dram_pre = 0; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_DRAM_RD])) - dram_reads = power_stats->get_dram_rd(1) - power_stats->dram_rd_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_DRAM_WR])) - dram_writes = power_stats->get_dram_wr(1) - power_stats->dram_wr_kernel; - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_DRAM_RD])) - dram_pre = power_stats->get_dram_pre(1) - power_stats->dram_pre_kernel; + float pipeline_duty_cycle = + ((*power_stats->m_average_pipeline_duty_cycle / (stat_sample_freq)) < 0.8) + ? ((*power_stats->m_average_pipeline_duty_cycle) / stat_sample_freq) + : 0.8; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_PIPE_DUTY])) + wrapper->set_duty_cycle_power(pipeline_duty_cycle); + else + wrapper->set_duty_cycle_power(std::stod(hw_data[HW_PIPE_DUTY])); - wrapper->set_mem_ctrl_power(dram_reads, dram_writes, dram_pre); + // Memory Controller - if(aggregate_power_stats){ - power_stats->ialu_acc_execution += power_stats->get_ialu_accessess(1); - power_stats->imul24_acc_execution += power_stats->get_intmul24_accessess(1); - power_stats->imul32_acc_execution += power_stats->get_intmul32_accessess(1); - power_stats->imul_acc_execution += power_stats->get_intmul_accessess(1); - power_stats->idiv_acc_execution += power_stats->get_intdiv_accessess(1); - power_stats->dp_acc_execution += power_stats->get_dp_accessess(1); - power_stats->dpmul_acc_execution += power_stats->get_dpmul_accessess(1); - power_stats->dpdiv_acc_execution += power_stats->get_dpdiv_accessess(1); - power_stats->fp_acc_execution += power_stats->get_fp_accessess(1); - power_stats->fpmul_acc_execution += power_stats->get_fpmul_accessess(1); - power_stats->fpdiv_acc_execution += power_stats->get_fpdiv_accessess(1); - power_stats->sqrt_acc_execution += power_stats->get_sqrt_accessess(1); - power_stats->log_acc_execution += power_stats->get_log_accessess(1); - power_stats->sin_acc_execution += power_stats->get_sin_accessess(1); - power_stats->exp_acc_execution += power_stats->get_exp_accessess(1); - power_stats->tensor_acc_execution += power_stats->get_tensor_accessess(1); - power_stats->tex_acc_execution += power_stats->get_tex_accessess(1); - power_stats->tot_fpu_acc_execution += power_stats->get_tot_fpu_accessess(1); - power_stats->tot_sfu_acc_execution += power_stats->get_tot_sfu_accessess(1); - power_stats->tot_threads_acc_execution += power_stats->get_tot_threads_kernel(1); - power_stats->tot_warps_acc_execution += power_stats->get_tot_warps_kernel(1); - - power_stats->sp_active_lanes_execution += (power_stats->get_sp_active_lanes() * shdr_config->num_shader() * shdr_config->gpgpu_num_sp_units); - power_stats->sfu_active_lanes_execution += (power_stats->get_sfu_active_lanes() * shdr_config->num_shader() * shdr_config->gpgpu_num_sp_units); + double dram_reads = std::stod(hw_data[HW_DRAM_RD]); + double dram_writes = std::stod(hw_data[HW_DRAM_WR]); + double dram_pre = 0; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_DRAM_RD])) + dram_reads = power_stats->get_dram_rd(1) - power_stats->dram_rd_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_DRAM_WR])) + dram_writes = power_stats->get_dram_wr(1) - power_stats->dram_wr_kernel; + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_DRAM_RD])) + dram_pre = power_stats->get_dram_pre(1) - power_stats->dram_pre_kernel; - wrapper->set_int_accesses(power_stats->ialu_acc_execution, - power_stats->imul24_acc_execution, - power_stats->imul32_acc_execution, - power_stats->imul_acc_execution, - power_stats->idiv_acc_execution); + wrapper->set_mem_ctrl_power(dram_reads, dram_writes, dram_pre); - wrapper->set_dp_accesses(power_stats->dp_acc_execution, - power_stats->dpmul_acc_execution, - power_stats->dpdiv_acc_execution); + if (aggregate_power_stats) { + power_stats->ialu_acc_execution += power_stats->get_ialu_accessess(1); + power_stats->imul24_acc_execution += power_stats->get_intmul24_accessess(1); + power_stats->imul32_acc_execution += power_stats->get_intmul32_accessess(1); + power_stats->imul_acc_execution += power_stats->get_intmul_accessess(1); + power_stats->idiv_acc_execution += power_stats->get_intdiv_accessess(1); + power_stats->dp_acc_execution += power_stats->get_dp_accessess(1); + power_stats->dpmul_acc_execution += power_stats->get_dpmul_accessess(1); + power_stats->dpdiv_acc_execution += power_stats->get_dpdiv_accessess(1); + power_stats->fp_acc_execution += power_stats->get_fp_accessess(1); + power_stats->fpmul_acc_execution += power_stats->get_fpmul_accessess(1); + power_stats->fpdiv_acc_execution += power_stats->get_fpdiv_accessess(1); + power_stats->sqrt_acc_execution += power_stats->get_sqrt_accessess(1); + power_stats->log_acc_execution += power_stats->get_log_accessess(1); + power_stats->sin_acc_execution += power_stats->get_sin_accessess(1); + power_stats->exp_acc_execution += power_stats->get_exp_accessess(1); + power_stats->tensor_acc_execution += power_stats->get_tensor_accessess(1); + power_stats->tex_acc_execution += power_stats->get_tex_accessess(1); + power_stats->tot_fpu_acc_execution += power_stats->get_tot_fpu_accessess(1); + power_stats->tot_sfu_acc_execution += power_stats->get_tot_sfu_accessess(1); + power_stats->tot_threads_acc_execution += + power_stats->get_tot_threads_kernel(1); + power_stats->tot_warps_acc_execution += + power_stats->get_tot_warps_kernel(1); - wrapper->set_fp_accesses(power_stats->fp_acc_execution, - power_stats->fpmul_acc_execution, - power_stats->fpdiv_acc_execution); + power_stats->sp_active_lanes_execution += + (power_stats->get_sp_active_lanes() * shdr_config->num_shader() * + shdr_config->gpgpu_num_sp_units); + power_stats->sfu_active_lanes_execution += + (power_stats->get_sfu_active_lanes() * shdr_config->num_shader() * + shdr_config->gpgpu_num_sp_units); - wrapper->set_trans_accesses(power_stats->sqrt_acc_execution, - power_stats->log_acc_execution, - power_stats->sin_acc_execution, - power_stats->exp_acc_execution); + wrapper->set_int_accesses( + power_stats->ialu_acc_execution, power_stats->imul24_acc_execution, + power_stats->imul32_acc_execution, power_stats->imul_acc_execution, + power_stats->idiv_acc_execution); - wrapper->set_tensor_accesses(power_stats->tensor_acc_execution); + wrapper->set_dp_accesses(power_stats->dp_acc_execution, + power_stats->dpmul_acc_execution, + power_stats->dpdiv_acc_execution); - wrapper->set_tex_accesses(power_stats->tex_acc_execution); + wrapper->set_fp_accesses(power_stats->fp_acc_execution, + power_stats->fpmul_acc_execution, + power_stats->fpdiv_acc_execution); - wrapper->set_exec_unit_power(power_stats->ialu_acc_execution, - power_stats->tot_fpu_acc_execution, - power_stats->tot_sfu_acc_execution); + wrapper->set_trans_accesses( + power_stats->sqrt_acc_execution, power_stats->log_acc_execution, + power_stats->sin_acc_execution, power_stats->exp_acc_execution); - wrapper->set_avg_active_threads((double)((double)power_stats->tot_threads_acc_execution / (double)power_stats->tot_warps_acc_execution)); + wrapper->set_tensor_accesses(power_stats->tensor_acc_execution); - // Average active lanes for sp and sfu pipelines - float avg_sp_active_lanes = - (power_stats->sp_active_lanes_execution) / shdr_config->num_shader() / shdr_config->gpgpu_num_sp_units / stat_sample_freq; - float avg_sfu_active_lanes = - (power_stats->sfu_active_lanes_execution) / shdr_config->num_shader() / shdr_config->gpgpu_num_sp_units / stat_sample_freq; - if(avg_sp_active_lanes >32.0 ) - avg_sp_active_lanes = 32.0; - if(avg_sfu_active_lanes >32.0 ) - avg_sfu_active_lanes = 32.0; - assert(avg_sp_active_lanes <= 32); - assert(avg_sfu_active_lanes <= 32); - wrapper->set_active_lanes_power(avg_sp_active_lanes, avg_sfu_active_lanes); - } - else{ - wrapper->set_int_accesses(power_stats->get_ialu_accessess(1), - power_stats->get_intmul24_accessess(1), - power_stats->get_intmul32_accessess(1), - power_stats->get_intmul_accessess(1), - power_stats->get_intdiv_accessess(1)); + wrapper->set_tex_accesses(power_stats->tex_acc_execution); - wrapper->set_dp_accesses(power_stats->get_dp_accessess(1), - power_stats->get_dpmul_accessess(1), - power_stats->get_dpdiv_accessess(1)); + wrapper->set_exec_unit_power(power_stats->ialu_acc_execution, + power_stats->tot_fpu_acc_execution, + power_stats->tot_sfu_acc_execution); - wrapper->set_fp_accesses(power_stats->get_fp_accessess(1), - power_stats->get_fpmul_accessess(1), - power_stats->get_fpdiv_accessess(1)); + wrapper->set_avg_active_threads( + (double)((double)power_stats->tot_threads_acc_execution / + (double)power_stats->tot_warps_acc_execution)); - wrapper->set_trans_accesses(power_stats->get_sqrt_accessess(1), - power_stats->get_log_accessess(1), - power_stats->get_sin_accessess(1), - power_stats->get_exp_accessess(1)); + // Average active lanes for sp and sfu pipelines + float avg_sp_active_lanes = + (power_stats->sp_active_lanes_execution) / shdr_config->num_shader() / + shdr_config->gpgpu_num_sp_units / stat_sample_freq; + float avg_sfu_active_lanes = + (power_stats->sfu_active_lanes_execution) / shdr_config->num_shader() / + shdr_config->gpgpu_num_sp_units / stat_sample_freq; + if (avg_sp_active_lanes > 32.0) avg_sp_active_lanes = 32.0; + if (avg_sfu_active_lanes > 32.0) avg_sfu_active_lanes = 32.0; + assert(avg_sp_active_lanes <= 32); + assert(avg_sfu_active_lanes <= 32); + wrapper->set_active_lanes_power(avg_sp_active_lanes, avg_sfu_active_lanes); + } else { + wrapper->set_int_accesses(power_stats->get_ialu_accessess(1), + power_stats->get_intmul24_accessess(1), + power_stats->get_intmul32_accessess(1), + power_stats->get_intmul_accessess(1), + power_stats->get_intdiv_accessess(1)); - wrapper->set_tensor_accesses(power_stats->get_tensor_accessess(1)); + wrapper->set_dp_accesses(power_stats->get_dp_accessess(1), + power_stats->get_dpmul_accessess(1), + power_stats->get_dpdiv_accessess(1)); - wrapper->set_tex_accesses(power_stats->get_tex_accessess(1)); + wrapper->set_fp_accesses(power_stats->get_fp_accessess(1), + power_stats->get_fpmul_accessess(1), + power_stats->get_fpdiv_accessess(1)); - wrapper->set_exec_unit_power(power_stats->get_tot_fpu_accessess(1), - power_stats->get_ialu_accessess(1), - power_stats->get_tot_sfu_accessess(1)); + wrapper->set_trans_accesses( + power_stats->get_sqrt_accessess(1), power_stats->get_log_accessess(1), + power_stats->get_sin_accessess(1), power_stats->get_exp_accessess(1)); - wrapper->set_avg_active_threads(power_stats->get_active_threads(1)); + wrapper->set_tensor_accesses(power_stats->get_tensor_accessess(1)); - // Average active lanes for sp and sfu pipelines - float avg_sp_active_lanes = - (power_stats->get_sp_active_lanes()) / stat_sample_freq; - float avg_sfu_active_lanes = - (power_stats->get_sfu_active_lanes()) / stat_sample_freq; - if(avg_sp_active_lanes >32.0 ) - avg_sp_active_lanes = 32.0; - if(avg_sfu_active_lanes >32.0 ) - avg_sfu_active_lanes = 32.0; - assert(avg_sp_active_lanes <= 32); - assert(avg_sfu_active_lanes <= 32); - wrapper->set_active_lanes_power(avg_sp_active_lanes, avg_sfu_active_lanes); - } + wrapper->set_tex_accesses(power_stats->get_tex_accessess(1)); - - double n_icnt_simt_to_mem = - (double) - (power_stats->get_icnt_simt_to_mem(1) - power_stats->noc_tr_kernel); // # flits from SIMT clusters - // to memory partitions - double n_icnt_mem_to_simt = - (double) - (power_stats->get_icnt_mem_to_simt(1)- power_stats->noc_rc_kernel); // # flits from memory - // partitions to SIMT clusters - if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_NOC])) - wrapper->set_NoC_power(n_icnt_mem_to_simt + n_icnt_simt_to_mem); // Number of flits traversing the interconnect from Accel-Sim - else - wrapper->set_NoC_power(std::stod(hw_data[HW_NOC])); // Number of flits traversing the interconnect from HW - - wrapper->compute(); + wrapper->set_exec_unit_power(power_stats->get_tot_fpu_accessess(1), + power_stats->get_ialu_accessess(1), + power_stats->get_tot_sfu_accessess(1)); - wrapper->update_components_power(); + wrapper->set_avg_active_threads(power_stats->get_active_threads(1)); - wrapper->power_metrics_calculations(); + // Average active lanes for sp and sfu pipelines + float avg_sp_active_lanes = + (power_stats->get_sp_active_lanes()) / stat_sample_freq; + float avg_sfu_active_lanes = + (power_stats->get_sfu_active_lanes()) / stat_sample_freq; + if (avg_sp_active_lanes > 32.0) avg_sp_active_lanes = 32.0; + if (avg_sfu_active_lanes > 32.0) avg_sfu_active_lanes = 32.0; + assert(avg_sp_active_lanes <= 32); + assert(avg_sfu_active_lanes <= 32); + wrapper->set_active_lanes_power(avg_sp_active_lanes, avg_sfu_active_lanes); + } - wrapper->dump(); - power_stats->l1r_hits_kernel = power_stats->get_l1d_read_hits(1); - power_stats->l1r_misses_kernel = power_stats->get_l1d_read_misses(1); - power_stats->l1w_hits_kernel = power_stats->get_l1d_write_hits(1); - power_stats->l1w_misses_kernel = power_stats->get_l1d_write_misses(1); - power_stats->shared_accesses_kernel = power_stats->get_const_accessess(1); - power_stats->cc_accesses_kernel = power_stats->get_shmem_access(1); - power_stats->dram_rd_kernel = power_stats->get_dram_rd(1); - power_stats->dram_wr_kernel = power_stats->get_dram_wr(1); - power_stats->dram_pre_kernel = power_stats->get_dram_pre(1); - power_stats->l1i_hits_kernel = power_stats->get_inst_c_hits(1); - power_stats->l1i_misses_kernel = power_stats->get_inst_c_misses(1); - power_stats->l2r_hits_kernel = power_stats->get_l2_read_hits(1); - power_stats->l2r_misses_kernel = power_stats->get_l2_read_misses(1); - power_stats->l2w_hits_kernel = power_stats->get_l2_write_hits(1); - power_stats->l2w_misses_kernel = power_stats->get_l2_write_misses(1); - power_stats->noc_tr_kernel = power_stats->get_icnt_simt_to_mem(1); - power_stats->noc_rc_kernel = power_stats->get_icnt_mem_to_simt(1); + double n_icnt_simt_to_mem = + (double)(power_stats->get_icnt_simt_to_mem(1) - + power_stats->noc_tr_kernel); // # flits from SIMT clusters + // to memory partitions + double n_icnt_mem_to_simt = + (double)(power_stats->get_icnt_mem_to_simt(1) - + power_stats->noc_rc_kernel); // # flits from memory + // partitions to SIMT clusters + if ((power_simulation_mode == 2) && + (accelwattch_hybrid_configuration[HW_NOC])) + wrapper->set_NoC_power( + n_icnt_mem_to_simt + + n_icnt_simt_to_mem); // Number of flits traversing the interconnect + // from Accel-Sim + else + wrapper->set_NoC_power( + std::stod(hw_data[HW_NOC])); // Number of flits traversing the + // interconnect from HW + + wrapper->compute(); + + wrapper->update_components_power(); + + wrapper->power_metrics_calculations(); + wrapper->dump(); + power_stats->l1r_hits_kernel = power_stats->get_l1d_read_hits(1); + power_stats->l1r_misses_kernel = power_stats->get_l1d_read_misses(1); + power_stats->l1w_hits_kernel = power_stats->get_l1d_write_hits(1); + power_stats->l1w_misses_kernel = power_stats->get_l1d_write_misses(1); + power_stats->shared_accesses_kernel = power_stats->get_const_accessess(1); + power_stats->cc_accesses_kernel = power_stats->get_shmem_access(1); + power_stats->dram_rd_kernel = power_stats->get_dram_rd(1); + power_stats->dram_wr_kernel = power_stats->get_dram_wr(1); + power_stats->dram_pre_kernel = power_stats->get_dram_pre(1); + power_stats->l1i_hits_kernel = power_stats->get_inst_c_hits(1); + power_stats->l1i_misses_kernel = power_stats->get_inst_c_misses(1); + power_stats->l2r_hits_kernel = power_stats->get_l2_read_hits(1); + power_stats->l2r_misses_kernel = power_stats->get_l2_read_misses(1); + power_stats->l2w_hits_kernel = power_stats->get_l2_write_hits(1); + power_stats->l2w_misses_kernel = power_stats->get_l2_write_misses(1); + power_stats->noc_tr_kernel = power_stats->get_icnt_simt_to_mem(1); + power_stats->noc_rc_kernel = power_stats->get_icnt_mem_to_simt(1); - power_stats->clear(); + power_stats->clear(); }
\ No newline at end of file diff --git a/src/gpgpu-sim/power_interface.h b/src/gpgpu-sim/power_interface.h index 1c6c510..3c043e6 100644 --- a/src/gpgpu-sim/power_interface.h +++ b/src/gpgpu-sim/power_interface.h @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler +// Hetherington, Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, +// Timothy G. Rogers The University of British Columbia, Northwestern +// University, Purdue University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -47,16 +48,18 @@ void mcpat_cycle(const gpgpu_sim_config &config, unsigned tot_cycle, unsigned cycle, unsigned tot_inst, unsigned inst, bool dvfs_enabled); -void calculate_hw_mcpat(const gpgpu_sim_config &config, - const shader_core_config *shdr_config, - class gpgpu_sim_wrapper *wrapper, - class power_stat_t *power_stats, unsigned stat_sample_freq, - unsigned tot_cycle, unsigned cycle, unsigned tot_inst, - unsigned inst, int power_simulation_mode, bool dvfs_enabled, - char* hwpowerfile, char* benchname, std::string executed_kernelname, - const bool *accelwattch_hybrid_configuration, bool aggregate_power_stats); +void calculate_hw_mcpat( + const gpgpu_sim_config &config, const shader_core_config *shdr_config, + class gpgpu_sim_wrapper *wrapper, class power_stat_t *power_stats, + unsigned stat_sample_freq, unsigned tot_cycle, unsigned cycle, + unsigned tot_inst, unsigned inst, int power_simulation_mode, + bool dvfs_enabled, char *hwpowerfile, char *benchname, + std::string executed_kernelname, + const bool *accelwattch_hybrid_configuration, bool aggregate_power_stats); -bool parse_hw_file(char* hwpowerfile, bool find_target_kernel, vector<string> &hw_data, char* benchname, std::string executed_kernelname); +bool parse_hw_file(char *hwpowerfile, bool find_target_kernel, + vector<string> &hw_data, char *benchname, + std::string executed_kernelname); void mcpat_reset_perf_count(class gpgpu_sim_wrapper *wrapper); diff --git a/src/gpgpu-sim/power_stat.cc b/src/gpgpu-sim/power_stat.cc index d0e673c..dead4a0 100644 --- a/src/gpgpu-sim/power_stat.cc +++ b/src/gpgpu-sim/power_stat.cc @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler +// Hetherington, Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, +// Timothy G. Rogers The University of British Columbia, Northwestern +// University, Purdue University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -56,60 +57,58 @@ power_mem_stat_t::power_mem_stat_t(const memory_config *mem_config, init(); } -void power_stat_t::clear(){ - for(unsigned i=0; i< NUM_STAT_IDX; ++i){ +void power_stat_t::clear() { + for (unsigned i = 0; i < NUM_STAT_IDX; ++i) { pwr_mem_stat->core_cache_stats[i].clear(); pwr_mem_stat->l2_cache_stats[i].clear(); - for(unsigned j=0; j<m_config->num_shader(); ++j){ - pwr_core_stat->m_pipeline_duty_cycle[i][j]=0; - pwr_core_stat->m_num_decoded_insn[i][j]=0; - pwr_core_stat->m_num_FPdecoded_insn[i][j]=0; - pwr_core_stat->m_num_INTdecoded_insn[i][j]=0; - pwr_core_stat->m_num_storequeued_insn[i][j]=0; - pwr_core_stat->m_num_loadqueued_insn[i][j]=0; - pwr_core_stat->m_num_tex_inst[i][j]=0; - pwr_core_stat->m_num_ialu_acesses[i][j]=0; - pwr_core_stat->m_num_fp_acesses[i][j]=0; - pwr_core_stat->m_num_imul_acesses[i][j]=0; - pwr_core_stat->m_num_imul24_acesses[i][j]=0; - pwr_core_stat->m_num_imul32_acesses[i][j]=0; - pwr_core_stat->m_num_fpmul_acesses[i][j]=0; - pwr_core_stat->m_num_idiv_acesses[i][j]=0; - pwr_core_stat->m_num_fpdiv_acesses[i][j]=0; - pwr_core_stat->m_num_dp_acesses[i][j]=0; - pwr_core_stat->m_num_dpmul_acesses[i][j]=0; - pwr_core_stat->m_num_dpdiv_acesses[i][j]=0; - pwr_core_stat->m_num_tensor_core_acesses[i][j]=0; - pwr_core_stat->m_num_const_acesses[i][j]=0; - pwr_core_stat->m_num_tex_acesses[i][j]=0; - pwr_core_stat->m_num_sp_acesses[i][j]=0; - pwr_core_stat->m_num_sfu_acesses[i][j]=0; - pwr_core_stat->m_num_sqrt_acesses[i][j]=0; - pwr_core_stat->m_num_log_acesses[i][j]=0; - pwr_core_stat->m_num_sin_acesses[i][j]=0; - pwr_core_stat->m_num_exp_acesses[i][j]=0; - pwr_core_stat->m_num_mem_acesses[i][j]=0; - pwr_core_stat->m_num_sp_committed[i][j]=0; - pwr_core_stat->m_num_sfu_committed[i][j]=0; - pwr_core_stat->m_num_mem_committed[i][j]=0; - pwr_core_stat->m_read_regfile_acesses[i][j]=0; - pwr_core_stat->m_write_regfile_acesses[i][j]=0; - pwr_core_stat->m_non_rf_operands[i][j]=0; - pwr_core_stat->m_active_sp_lanes[i][j]=0; - pwr_core_stat->m_active_sfu_lanes[i][j]=0; - pwr_core_stat->m_active_exu_threads[i][j]=0; - pwr_core_stat->m_active_exu_warps[i][j]=0; + for (unsigned j = 0; j < m_config->num_shader(); ++j) { + pwr_core_stat->m_pipeline_duty_cycle[i][j] = 0; + pwr_core_stat->m_num_decoded_insn[i][j] = 0; + pwr_core_stat->m_num_FPdecoded_insn[i][j] = 0; + pwr_core_stat->m_num_INTdecoded_insn[i][j] = 0; + pwr_core_stat->m_num_storequeued_insn[i][j] = 0; + pwr_core_stat->m_num_loadqueued_insn[i][j] = 0; + pwr_core_stat->m_num_tex_inst[i][j] = 0; + pwr_core_stat->m_num_ialu_acesses[i][j] = 0; + pwr_core_stat->m_num_fp_acesses[i][j] = 0; + pwr_core_stat->m_num_imul_acesses[i][j] = 0; + pwr_core_stat->m_num_imul24_acesses[i][j] = 0; + pwr_core_stat->m_num_imul32_acesses[i][j] = 0; + pwr_core_stat->m_num_fpmul_acesses[i][j] = 0; + pwr_core_stat->m_num_idiv_acesses[i][j] = 0; + pwr_core_stat->m_num_fpdiv_acesses[i][j] = 0; + pwr_core_stat->m_num_dp_acesses[i][j] = 0; + pwr_core_stat->m_num_dpmul_acesses[i][j] = 0; + pwr_core_stat->m_num_dpdiv_acesses[i][j] = 0; + pwr_core_stat->m_num_tensor_core_acesses[i][j] = 0; + pwr_core_stat->m_num_const_acesses[i][j] = 0; + pwr_core_stat->m_num_tex_acesses[i][j] = 0; + pwr_core_stat->m_num_sp_acesses[i][j] = 0; + pwr_core_stat->m_num_sfu_acesses[i][j] = 0; + pwr_core_stat->m_num_sqrt_acesses[i][j] = 0; + pwr_core_stat->m_num_log_acesses[i][j] = 0; + pwr_core_stat->m_num_sin_acesses[i][j] = 0; + pwr_core_stat->m_num_exp_acesses[i][j] = 0; + pwr_core_stat->m_num_mem_acesses[i][j] = 0; + pwr_core_stat->m_num_sp_committed[i][j] = 0; + pwr_core_stat->m_num_sfu_committed[i][j] = 0; + pwr_core_stat->m_num_mem_committed[i][j] = 0; + pwr_core_stat->m_read_regfile_acesses[i][j] = 0; + pwr_core_stat->m_write_regfile_acesses[i][j] = 0; + pwr_core_stat->m_non_rf_operands[i][j] = 0; + pwr_core_stat->m_active_sp_lanes[i][j] = 0; + pwr_core_stat->m_active_sfu_lanes[i][j] = 0; + pwr_core_stat->m_active_exu_threads[i][j] = 0; + pwr_core_stat->m_active_exu_warps[i][j] = 0; } for (unsigned j = 0; j < m_mem_config->m_n_mem; ++j) { - pwr_mem_stat->n_rd[i][j]=0; - pwr_mem_stat->n_wr[i][j]=0; - pwr_mem_stat->n_pre[i][j]=0; + pwr_mem_stat->n_rd[i][j] = 0; + pwr_mem_stat->n_wr[i][j] = 0; + pwr_mem_stat->n_pre[i][j] = 0; } } } - - void power_mem_stat_t::init() { shmem_access[CURRENT_STAT_IDX] = m_core_stats->gpgpu_n_shmem_bank_access; // Shared memory access @@ -175,7 +174,8 @@ void power_mem_stat_t::print(FILE *fout) const { unsigned total_mem_writes = 0; for (unsigned i = 0; i < m_config->m_n_mem; ++i) { total_mem_reads += n_rd[CURRENT_STAT_IDX][i]; - total_mem_writes += n_wr[CURRENT_STAT_IDX][i] + n_wr_WB[CURRENT_STAT_IDX][i]; + total_mem_writes += + n_wr[CURRENT_STAT_IDX][i] + n_wr_WB[CURRENT_STAT_IDX][i]; } fprintf(fout, "Total memory controller accesses: %u\n", total_mem_reads + total_mem_writes); @@ -205,165 +205,272 @@ void power_core_stat_t::print(FILE *fout) { // per core statistics fprintf(fout, "Power Metrics: \n"); for (unsigned i = 0; i < m_config->num_shader(); i++) { - fprintf(fout,"core %u:\n",i); - fprintf(fout,"\tpipeline duty cycle =%f\n",m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal Deocded Instructions=%u\n",m_num_decoded_insn[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal FP Deocded Instructions=%u\n",m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal INT Deocded Instructions=%u\n",m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal LOAD Queued Instructions=%u\n",m_num_loadqueued_insn[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal STORE Queued Instructions=%u\n",m_num_storequeued_insn[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal IALU Acesses=%f\n",m_num_ialu_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal FP Acesses=%f\n",m_num_fp_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal DP Acesses=%f\n",m_num_dp_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal IMUL Acesses=%f\n",m_num_imul_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal IMUL24 Acesses=%f\n",m_num_imul24_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal IMUL32 Acesses=%f\n",m_num_imul32_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal IDIV Acesses=%f\n",m_num_idiv_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal FPMUL Acesses=%f\n",m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal DPMUL Acesses=%f\n",m_num_dpmul_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal SQRT Acesses=%f\n",m_num_sqrt_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal LOG Acesses=%f\n",m_num_log_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal SIN Acesses=%f\n",m_num_sin_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal EXP Acesses=%f\n",m_num_exp_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal FPDIV Acesses=%f\n",m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal DPDIV Acesses=%f\n",m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal TENSOR Acesses=%f\n",m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal CONST Acesses=%f\n",m_num_const_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal TEX Acesses=%f\n",m_num_tex_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal SFU Acesses=%f\n",m_num_sfu_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal SP Acesses=%f\n",m_num_sp_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal MEM Acesses=%f\n",m_num_mem_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal SFU Commissions=%u\n",m_num_sfu_committed[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal SP Commissions=%u\n",m_num_sp_committed[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal MEM Commissions=%u\n",m_num_mem_committed[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal REG Reads=%u\n",m_read_regfile_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal REG Writes=%u\n",m_write_regfile_acesses[CURRENT_STAT_IDX][i]); - fprintf(fout,"\tTotal NON REG=%u\n",m_non_rf_operands[CURRENT_STAT_IDX][i]); + fprintf(fout, "core %u:\n", i); + fprintf(fout, "\tpipeline duty cycle =%f\n", + m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal Deocded Instructions=%u\n", + m_num_decoded_insn[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal FP Deocded Instructions=%u\n", + m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal INT Deocded Instructions=%u\n", + m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal LOAD Queued Instructions=%u\n", + m_num_loadqueued_insn[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal STORE Queued Instructions=%u\n", + m_num_storequeued_insn[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal IALU Acesses=%f\n", + m_num_ialu_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal FP Acesses=%f\n", + m_num_fp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal DP Acesses=%f\n", + m_num_dp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal IMUL Acesses=%f\n", + m_num_imul_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal IMUL24 Acesses=%f\n", + m_num_imul24_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal IMUL32 Acesses=%f\n", + m_num_imul32_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal IDIV Acesses=%f\n", + m_num_idiv_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal FPMUL Acesses=%f\n", + m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal DPMUL Acesses=%f\n", + m_num_dpmul_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal SQRT Acesses=%f\n", + m_num_sqrt_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal LOG Acesses=%f\n", + m_num_log_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal SIN Acesses=%f\n", + m_num_sin_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal EXP Acesses=%f\n", + m_num_exp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal FPDIV Acesses=%f\n", + m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal DPDIV Acesses=%f\n", + m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal TENSOR Acesses=%f\n", + m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal CONST Acesses=%f\n", + m_num_const_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal TEX Acesses=%f\n", + m_num_tex_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal SFU Acesses=%f\n", + m_num_sfu_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal SP Acesses=%f\n", + m_num_sp_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal MEM Acesses=%f\n", + m_num_mem_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal SFU Commissions=%u\n", + m_num_sfu_committed[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal SP Commissions=%u\n", + m_num_sp_committed[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal MEM Commissions=%u\n", + m_num_mem_committed[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal REG Reads=%u\n", + m_read_regfile_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal REG Writes=%u\n", + m_write_regfile_acesses[CURRENT_STAT_IDX][i]); + fprintf(fout, "\tTotal NON REG=%u\n", + m_non_rf_operands[CURRENT_STAT_IDX][i]); } } void power_core_stat_t::init() { - m_pipeline_duty_cycle[CURRENT_STAT_IDX]=m_core_stats->m_pipeline_duty_cycle; - m_num_decoded_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_decoded_insn; - m_num_FPdecoded_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_FPdecoded_insn; - m_num_INTdecoded_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_INTdecoded_insn; - m_num_storequeued_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_storequeued_insn; - m_num_loadqueued_insn[CURRENT_STAT_IDX]=m_core_stats->m_num_loadqueued_insn; - m_num_ialu_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_ialu_acesses; - m_num_fp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_fp_acesses; - m_num_imul_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_imul_acesses; - m_num_imul24_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_imul24_acesses; - m_num_imul32_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_imul32_acesses; - m_num_fpmul_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_fpmul_acesses; - m_num_idiv_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_idiv_acesses; - m_num_fpdiv_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_fpdiv_acesses; - m_num_dp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_dp_acesses; - m_num_dpmul_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_dpmul_acesses; - m_num_dpdiv_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_dpdiv_acesses; - m_num_sp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sp_acesses; - m_num_sfu_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sfu_acesses; - m_num_sqrt_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sqrt_acesses; - m_num_log_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_log_acesses; - m_num_sin_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_sin_acesses; - m_num_exp_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_exp_acesses; - m_num_tensor_core_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_tensor_core_acesses; - m_num_const_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_const_acesses; - m_num_tex_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_tex_acesses; - m_num_mem_acesses[CURRENT_STAT_IDX]=m_core_stats->m_num_mem_acesses; - m_num_sp_committed[CURRENT_STAT_IDX]=m_core_stats->m_num_sp_committed; - m_num_sfu_committed[CURRENT_STAT_IDX]=m_core_stats->m_num_sfu_committed; - m_num_mem_committed[CURRENT_STAT_IDX]=m_core_stats->m_num_mem_committed; - m_read_regfile_acesses[CURRENT_STAT_IDX]=m_core_stats->m_read_regfile_acesses; - m_write_regfile_acesses[CURRENT_STAT_IDX]=m_core_stats->m_write_regfile_acesses; - m_non_rf_operands[CURRENT_STAT_IDX]=m_core_stats->m_non_rf_operands; - m_active_sp_lanes[CURRENT_STAT_IDX]=m_core_stats->m_active_sp_lanes; - m_active_sfu_lanes[CURRENT_STAT_IDX]=m_core_stats->m_active_sfu_lanes; - m_active_exu_threads[CURRENT_STAT_IDX]=m_core_stats->m_active_exu_threads; - m_active_exu_warps[CURRENT_STAT_IDX]=m_core_stats->m_active_exu_warps; - m_num_tex_inst[CURRENT_STAT_IDX]=m_core_stats->m_num_tex_inst; - - m_pipeline_duty_cycle[PREV_STAT_IDX]=(float*)calloc(m_config->num_shader(),sizeof(float)); - m_num_decoded_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_FPdecoded_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_INTdecoded_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_storequeued_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_loadqueued_insn[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_tex_inst[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - - m_num_ialu_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_fp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_imul_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_imul24_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_imul32_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_fpmul_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_idiv_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_fpdiv_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_dp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_dpmul_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_dpdiv_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_tensor_core_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_const_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_tex_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_sp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_sfu_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_sqrt_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_log_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_sin_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_exp_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_mem_acesses[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_num_sp_committed[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_sfu_committed[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_num_mem_committed[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_read_regfile_acesses[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_write_regfile_acesses[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_non_rf_operands[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_active_sp_lanes[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_active_sfu_lanes[PREV_STAT_IDX]=(unsigned *)calloc(m_config->num_shader(),sizeof(unsigned)); - m_active_exu_threads[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); - m_active_exu_warps[PREV_STAT_IDX]=(double *)calloc(m_config->num_shader(),sizeof(double)); + m_pipeline_duty_cycle[CURRENT_STAT_IDX] = m_core_stats->m_pipeline_duty_cycle; + m_num_decoded_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_decoded_insn; + m_num_FPdecoded_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_FPdecoded_insn; + m_num_INTdecoded_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_INTdecoded_insn; + m_num_storequeued_insn[CURRENT_STAT_IDX] = + m_core_stats->m_num_storequeued_insn; + m_num_loadqueued_insn[CURRENT_STAT_IDX] = m_core_stats->m_num_loadqueued_insn; + m_num_ialu_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_ialu_acesses; + m_num_fp_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_fp_acesses; + m_num_imul_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_imul_acesses; + m_num_imul24_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_imul24_acesses; + m_num_imul32_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_imul32_acesses; + m_num_fpmul_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_fpmul_acesses; + m_num_idiv_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_idiv_acesses; + m_num_fpdiv_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_fpdiv_acesses; + m_num_dp_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_dp_acesses; + m_num_dpmul_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_dpmul_acesses; + m_num_dpdiv_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_dpdiv_acesses; + m_num_sp_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_sp_acesses; + m_num_sfu_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_sfu_acesses; + m_num_sqrt_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_sqrt_acesses; + m_num_log_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_log_acesses; + m_num_sin_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_sin_acesses; + m_num_exp_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_exp_acesses; + m_num_tensor_core_acesses[CURRENT_STAT_IDX] = + m_core_stats->m_num_tensor_core_acesses; + m_num_const_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_const_acesses; + m_num_tex_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_tex_acesses; + m_num_mem_acesses[CURRENT_STAT_IDX] = m_core_stats->m_num_mem_acesses; + m_num_sp_committed[CURRENT_STAT_IDX] = m_core_stats->m_num_sp_committed; + m_num_sfu_committed[CURRENT_STAT_IDX] = m_core_stats->m_num_sfu_committed; + m_num_mem_committed[CURRENT_STAT_IDX] = m_core_stats->m_num_mem_committed; + m_read_regfile_acesses[CURRENT_STAT_IDX] = + m_core_stats->m_read_regfile_acesses; + m_write_regfile_acesses[CURRENT_STAT_IDX] = + m_core_stats->m_write_regfile_acesses; + m_non_rf_operands[CURRENT_STAT_IDX] = m_core_stats->m_non_rf_operands; + m_active_sp_lanes[CURRENT_STAT_IDX] = m_core_stats->m_active_sp_lanes; + m_active_sfu_lanes[CURRENT_STAT_IDX] = m_core_stats->m_active_sfu_lanes; + m_active_exu_threads[CURRENT_STAT_IDX] = m_core_stats->m_active_exu_threads; + m_active_exu_warps[CURRENT_STAT_IDX] = m_core_stats->m_active_exu_warps; + m_num_tex_inst[CURRENT_STAT_IDX] = m_core_stats->m_num_tex_inst; + m_pipeline_duty_cycle[PREV_STAT_IDX] = + (float *)calloc(m_config->num_shader(), sizeof(float)); + m_num_decoded_insn[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_FPdecoded_insn[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_INTdecoded_insn[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_storequeued_insn[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_loadqueued_insn[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_tex_inst[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_ialu_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_fp_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_imul_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_imul24_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_imul32_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_fpmul_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_idiv_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_fpdiv_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_dp_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_dpmul_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_dpdiv_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_tensor_core_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_const_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_tex_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_sp_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_sfu_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_sqrt_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_log_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_sin_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_exp_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_mem_acesses[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_num_sp_committed[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_sfu_committed[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_num_mem_committed[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_read_regfile_acesses[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_write_regfile_acesses[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_non_rf_operands[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_active_sp_lanes[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_active_sfu_lanes[PREV_STAT_IDX] = + (unsigned *)calloc(m_config->num_shader(), sizeof(unsigned)); + m_active_exu_threads[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); + m_active_exu_warps[PREV_STAT_IDX] = + (double *)calloc(m_config->num_shader(), sizeof(double)); } void power_core_stat_t::save_stats() { for (unsigned i = 0; i < m_config->num_shader(); ++i) { - m_pipeline_duty_cycle[PREV_STAT_IDX][i]=m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]; - m_num_decoded_insn[PREV_STAT_IDX][i]= m_num_decoded_insn[CURRENT_STAT_IDX][i]; - m_num_FPdecoded_insn[PREV_STAT_IDX][i]=m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]; - m_num_INTdecoded_insn[PREV_STAT_IDX][i]=m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]; - m_num_storequeued_insn[PREV_STAT_IDX][i]=m_num_storequeued_insn[CURRENT_STAT_IDX][i]; - m_num_loadqueued_insn[PREV_STAT_IDX][i]=m_num_loadqueued_insn[CURRENT_STAT_IDX][i]; - m_num_ialu_acesses[PREV_STAT_IDX][i]=m_num_ialu_acesses[CURRENT_STAT_IDX][i]; - m_num_fp_acesses[PREV_STAT_IDX][i]=m_num_fp_acesses[CURRENT_STAT_IDX][i]; - m_num_tex_inst[PREV_STAT_IDX][i]=m_num_tex_inst[CURRENT_STAT_IDX][i]; - m_num_imul_acesses[PREV_STAT_IDX][i]=m_num_imul_acesses[CURRENT_STAT_IDX][i]; - m_num_imul24_acesses[PREV_STAT_IDX][i]=m_num_imul24_acesses[CURRENT_STAT_IDX][i]; - m_num_imul32_acesses[PREV_STAT_IDX][i]=m_num_imul32_acesses[CURRENT_STAT_IDX][i]; - m_num_fpmul_acesses[PREV_STAT_IDX][i]=m_num_fpmul_acesses[CURRENT_STAT_IDX][i]; - m_num_idiv_acesses[PREV_STAT_IDX][i]=m_num_idiv_acesses[CURRENT_STAT_IDX][i]; - m_num_fpdiv_acesses[PREV_STAT_IDX][i]=m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]; - m_num_sp_acesses[PREV_STAT_IDX][i]=m_num_sp_acesses[CURRENT_STAT_IDX][i]; - m_num_sfu_acesses[PREV_STAT_IDX][i]=m_num_sfu_acesses[CURRENT_STAT_IDX][i]; - m_num_sqrt_acesses[PREV_STAT_IDX][i]=m_num_sqrt_acesses[CURRENT_STAT_IDX][i]; - m_num_log_acesses[PREV_STAT_IDX][i]=m_num_log_acesses[CURRENT_STAT_IDX][i]; - m_num_sin_acesses[PREV_STAT_IDX][i]=m_num_sin_acesses[CURRENT_STAT_IDX][i]; - m_num_exp_acesses[PREV_STAT_IDX][i]=m_num_exp_acesses[CURRENT_STAT_IDX][i]; - m_num_dp_acesses[PREV_STAT_IDX][i]=m_num_dp_acesses[CURRENT_STAT_IDX][i]; - m_num_dpmul_acesses[PREV_STAT_IDX][i]=m_num_dpmul_acesses[CURRENT_STAT_IDX][i]; - m_num_dpdiv_acesses[PREV_STAT_IDX][i]=m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]; - m_num_tensor_core_acesses[PREV_STAT_IDX][i]=m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]; - m_num_const_acesses[PREV_STAT_IDX][i]=m_num_const_acesses[CURRENT_STAT_IDX][i]; - m_num_tex_acesses[PREV_STAT_IDX][i]=m_num_tex_acesses[CURRENT_STAT_IDX][i]; - m_num_mem_acesses[PREV_STAT_IDX][i]=m_num_mem_acesses[CURRENT_STAT_IDX][i]; - m_num_sp_committed[PREV_STAT_IDX][i]=m_num_sp_committed[CURRENT_STAT_IDX][i]; - m_num_sfu_committed[PREV_STAT_IDX][i]=m_num_sfu_committed[CURRENT_STAT_IDX][i]; - m_num_mem_committed[PREV_STAT_IDX][i]=m_num_mem_committed[CURRENT_STAT_IDX][i]; - m_read_regfile_acesses[PREV_STAT_IDX][i]=m_read_regfile_acesses[CURRENT_STAT_IDX][i]; - m_write_regfile_acesses[PREV_STAT_IDX][i]=m_write_regfile_acesses[CURRENT_STAT_IDX][i]; - m_non_rf_operands[PREV_STAT_IDX][i]=m_non_rf_operands[CURRENT_STAT_IDX][i]; - m_active_sp_lanes[PREV_STAT_IDX][i]=m_active_sp_lanes[CURRENT_STAT_IDX][i]; - m_active_sfu_lanes[PREV_STAT_IDX][i]=m_active_sfu_lanes[CURRENT_STAT_IDX][i]; - m_active_exu_threads[PREV_STAT_IDX][i]=m_active_exu_threads[CURRENT_STAT_IDX][i]; - m_active_exu_warps[PREV_STAT_IDX][i]=m_active_exu_warps[CURRENT_STAT_IDX][i]; + m_pipeline_duty_cycle[PREV_STAT_IDX][i] = + m_pipeline_duty_cycle[CURRENT_STAT_IDX][i]; + m_num_decoded_insn[PREV_STAT_IDX][i] = + m_num_decoded_insn[CURRENT_STAT_IDX][i]; + m_num_FPdecoded_insn[PREV_STAT_IDX][i] = + m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]; + m_num_INTdecoded_insn[PREV_STAT_IDX][i] = + m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]; + m_num_storequeued_insn[PREV_STAT_IDX][i] = + m_num_storequeued_insn[CURRENT_STAT_IDX][i]; + m_num_loadqueued_insn[PREV_STAT_IDX][i] = + m_num_loadqueued_insn[CURRENT_STAT_IDX][i]; + m_num_ialu_acesses[PREV_STAT_IDX][i] = + m_num_ialu_acesses[CURRENT_STAT_IDX][i]; + m_num_fp_acesses[PREV_STAT_IDX][i] = m_num_fp_acesses[CURRENT_STAT_IDX][i]; + m_num_tex_inst[PREV_STAT_IDX][i] = m_num_tex_inst[CURRENT_STAT_IDX][i]; + m_num_imul_acesses[PREV_STAT_IDX][i] = + m_num_imul_acesses[CURRENT_STAT_IDX][i]; + m_num_imul24_acesses[PREV_STAT_IDX][i] = + m_num_imul24_acesses[CURRENT_STAT_IDX][i]; + m_num_imul32_acesses[PREV_STAT_IDX][i] = + m_num_imul32_acesses[CURRENT_STAT_IDX][i]; + m_num_fpmul_acesses[PREV_STAT_IDX][i] = + m_num_fpmul_acesses[CURRENT_STAT_IDX][i]; + m_num_idiv_acesses[PREV_STAT_IDX][i] = + m_num_idiv_acesses[CURRENT_STAT_IDX][i]; + m_num_fpdiv_acesses[PREV_STAT_IDX][i] = + m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]; + m_num_sp_acesses[PREV_STAT_IDX][i] = m_num_sp_acesses[CURRENT_STAT_IDX][i]; + m_num_sfu_acesses[PREV_STAT_IDX][i] = + m_num_sfu_acesses[CURRENT_STAT_IDX][i]; + m_num_sqrt_acesses[PREV_STAT_IDX][i] = + m_num_sqrt_acesses[CURRENT_STAT_IDX][i]; + m_num_log_acesses[PREV_STAT_IDX][i] = + m_num_log_acesses[CURRENT_STAT_IDX][i]; + m_num_sin_acesses[PREV_STAT_IDX][i] = + m_num_sin_acesses[CURRENT_STAT_IDX][i]; + m_num_exp_acesses[PREV_STAT_IDX][i] = + m_num_exp_acesses[CURRENT_STAT_IDX][i]; + m_num_dp_acesses[PREV_STAT_IDX][i] = m_num_dp_acesses[CURRENT_STAT_IDX][i]; + m_num_dpmul_acesses[PREV_STAT_IDX][i] = + m_num_dpmul_acesses[CURRENT_STAT_IDX][i]; + m_num_dpdiv_acesses[PREV_STAT_IDX][i] = + m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]; + m_num_tensor_core_acesses[PREV_STAT_IDX][i] = + m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]; + m_num_const_acesses[PREV_STAT_IDX][i] = + m_num_const_acesses[CURRENT_STAT_IDX][i]; + m_num_tex_acesses[PREV_STAT_IDX][i] = + m_num_tex_acesses[CURRENT_STAT_IDX][i]; + m_num_mem_acesses[PREV_STAT_IDX][i] = + m_num_mem_acesses[CURRENT_STAT_IDX][i]; + m_num_sp_committed[PREV_STAT_IDX][i] = + m_num_sp_committed[CURRENT_STAT_IDX][i]; + m_num_sfu_committed[PREV_STAT_IDX][i] = + m_num_sfu_committed[CURRENT_STAT_IDX][i]; + m_num_mem_committed[PREV_STAT_IDX][i] = + m_num_mem_committed[CURRENT_STAT_IDX][i]; + m_read_regfile_acesses[PREV_STAT_IDX][i] = + m_read_regfile_acesses[CURRENT_STAT_IDX][i]; + m_write_regfile_acesses[PREV_STAT_IDX][i] = + m_write_regfile_acesses[CURRENT_STAT_IDX][i]; + m_non_rf_operands[PREV_STAT_IDX][i] = + m_non_rf_operands[CURRENT_STAT_IDX][i]; + m_active_sp_lanes[PREV_STAT_IDX][i] = + m_active_sp_lanes[CURRENT_STAT_IDX][i]; + m_active_sfu_lanes[PREV_STAT_IDX][i] = + m_active_sfu_lanes[CURRENT_STAT_IDX][i]; + m_active_exu_threads[PREV_STAT_IDX][i] = + m_active_exu_threads[CURRENT_STAT_IDX][i]; + m_active_exu_warps[PREV_STAT_IDX][i] = + m_active_exu_warps[CURRENT_STAT_IDX][i]; } } @@ -390,12 +497,12 @@ power_stat_t::power_stat_t(const shader_core_config *shader_config, dram_rd_kernel = 0; dram_wr_kernel = 0; dram_pre_kernel = 0; - l1i_hits_kernel =0; - l1i_misses_kernel =0; - l2r_hits_kernel =0; - l2r_misses_kernel =0; - l2w_hits_kernel =0; - l2w_misses_kernel =0; + l1i_hits_kernel = 0; + l1i_misses_kernel = 0; + l2r_hits_kernel = 0; + l2r_misses_kernel = 0; + l2w_hits_kernel = 0; + l2w_misses_kernel = 0; noc_tr_kernel = 0; noc_rc_kernel = 0; diff --git a/src/gpgpu-sim/power_stat.h b/src/gpgpu-sim/power_stat.h index d40f1d9..13f144a 100644 --- a/src/gpgpu-sim/power_stat.h +++ b/src/gpgpu-sim/power_stat.h @@ -1,17 +1,18 @@ -// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler +// Hetherington, Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan, +// Timothy G. Rogers The University of British Columbia, Northwestern +// University, Purdue University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -53,40 +54,40 @@ struct shader_core_power_stats_pod { unsigned *m_num_INTdecoded_insn[NUM_STAT_IDX]; // number of instructions committed // by this shader core - unsigned *m_num_storequeued_insn[NUM_STAT_IDX]; - unsigned *m_num_loadqueued_insn[NUM_STAT_IDX]; - unsigned *m_num_tex_inst[NUM_STAT_IDX]; - double *m_num_ialu_acesses[NUM_STAT_IDX]; - double *m_num_fp_acesses[NUM_STAT_IDX]; - double *m_num_imul_acesses[NUM_STAT_IDX]; - double *m_num_imul32_acesses[NUM_STAT_IDX]; - double *m_num_imul24_acesses[NUM_STAT_IDX]; - double *m_num_fpmul_acesses[NUM_STAT_IDX]; - double *m_num_idiv_acesses[NUM_STAT_IDX]; - double *m_num_fpdiv_acesses[NUM_STAT_IDX]; - double *m_num_dp_acesses[NUM_STAT_IDX]; - double *m_num_dpmul_acesses[NUM_STAT_IDX]; - double *m_num_dpdiv_acesses[NUM_STAT_IDX]; - double *m_num_sp_acesses[NUM_STAT_IDX]; - double *m_num_sfu_acesses[NUM_STAT_IDX]; - double *m_num_sqrt_acesses[NUM_STAT_IDX]; - double *m_num_log_acesses[NUM_STAT_IDX]; - double *m_num_sin_acesses[NUM_STAT_IDX]; - double *m_num_exp_acesses[NUM_STAT_IDX]; - double *m_num_tensor_core_acesses[NUM_STAT_IDX]; - double *m_num_const_acesses[NUM_STAT_IDX]; - double *m_num_tex_acesses[NUM_STAT_IDX]; - double *m_num_mem_acesses[NUM_STAT_IDX]; - unsigned *m_num_sp_committed[NUM_STAT_IDX]; - unsigned *m_num_sfu_committed[NUM_STAT_IDX]; - unsigned *m_num_mem_committed[NUM_STAT_IDX]; - unsigned *m_active_sp_lanes[NUM_STAT_IDX]; - unsigned *m_active_sfu_lanes[NUM_STAT_IDX]; - double *m_active_exu_threads[NUM_STAT_IDX]; - double *m_active_exu_warps[NUM_STAT_IDX]; - unsigned *m_read_regfile_acesses[NUM_STAT_IDX]; - unsigned *m_write_regfile_acesses[NUM_STAT_IDX]; - unsigned *m_non_rf_operands[NUM_STAT_IDX]; + unsigned *m_num_storequeued_insn[NUM_STAT_IDX]; + unsigned *m_num_loadqueued_insn[NUM_STAT_IDX]; + unsigned *m_num_tex_inst[NUM_STAT_IDX]; + double *m_num_ialu_acesses[NUM_STAT_IDX]; + double *m_num_fp_acesses[NUM_STAT_IDX]; + double *m_num_imul_acesses[NUM_STAT_IDX]; + double *m_num_imul32_acesses[NUM_STAT_IDX]; + double *m_num_imul24_acesses[NUM_STAT_IDX]; + double *m_num_fpmul_acesses[NUM_STAT_IDX]; + double *m_num_idiv_acesses[NUM_STAT_IDX]; + double *m_num_fpdiv_acesses[NUM_STAT_IDX]; + double *m_num_dp_acesses[NUM_STAT_IDX]; + double *m_num_dpmul_acesses[NUM_STAT_IDX]; + double *m_num_dpdiv_acesses[NUM_STAT_IDX]; + double *m_num_sp_acesses[NUM_STAT_IDX]; + double *m_num_sfu_acesses[NUM_STAT_IDX]; + double *m_num_sqrt_acesses[NUM_STAT_IDX]; + double *m_num_log_acesses[NUM_STAT_IDX]; + double *m_num_sin_acesses[NUM_STAT_IDX]; + double *m_num_exp_acesses[NUM_STAT_IDX]; + double *m_num_tensor_core_acesses[NUM_STAT_IDX]; + double *m_num_const_acesses[NUM_STAT_IDX]; + double *m_num_tex_acesses[NUM_STAT_IDX]; + double *m_num_mem_acesses[NUM_STAT_IDX]; + unsigned *m_num_sp_committed[NUM_STAT_IDX]; + unsigned *m_num_sfu_committed[NUM_STAT_IDX]; + unsigned *m_num_mem_committed[NUM_STAT_IDX]; + unsigned *m_active_sp_lanes[NUM_STAT_IDX]; + unsigned *m_active_sfu_lanes[NUM_STAT_IDX]; + double *m_active_exu_threads[NUM_STAT_IDX]; + double *m_active_exu_warps[NUM_STAT_IDX]; + unsigned *m_read_regfile_acesses[NUM_STAT_IDX]; + unsigned *m_write_regfile_acesses[NUM_STAT_IDX]; + unsigned *m_non_rf_operands[NUM_STAT_IDX]; }; class power_core_stat_t : public shader_core_power_stats_pod { @@ -97,7 +98,6 @@ class power_core_stat_t : public shader_core_power_stats_pod { void print(FILE *fout); void init(); void save_stats(); - private: shader_core_stats *m_core_stats; @@ -206,35 +206,37 @@ class power_stat_t { double get_total_inst(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_decoded_insn[CURRENT_STAT_IDX][i]); else total_inst += (pwr_core_stat->m_num_decoded_insn[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_decoded_insn[PREV_STAT_IDX][i]); + (pwr_core_stat->m_num_decoded_insn[PREV_STAT_IDX][i]); } return total_inst; } double get_total_int_inst(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += - (pwr_core_stat->m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); - else + if (aggregate_stat) total_inst += - (pwr_core_stat->m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_INTdecoded_insn[PREV_STAT_IDX][i]); + (pwr_core_stat->m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_INTdecoded_insn[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_INTdecoded_insn[PREV_STAT_IDX][i]); } return total_inst; } double get_total_fp_inst(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_FPdecoded_insn[PREV_STAT_IDX][i]); + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_FPdecoded_insn[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_FPdecoded_insn[PREV_STAT_IDX][i]); } return total_inst; } @@ -283,43 +285,45 @@ class power_stat_t { double get_committed_inst(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) + - (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) + - (pwr_core_stat->m_num_sp_committed[CURRENT_STAT_IDX][i]); + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_sp_committed[CURRENT_STAT_IDX][i]); else - total_inst += (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_mem_committed[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_sfu_committed[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_sp_committed[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_sp_committed[PREV_STAT_IDX][i]); + total_inst += + (pwr_core_stat->m_num_mem_committed[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_mem_committed[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_sfu_committed[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sfu_committed[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_sp_committed[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sp_committed[PREV_STAT_IDX][i]); } return total_inst; } double get_regfile_reads(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += - (pwr_core_stat->m_read_regfile_acesses[CURRENT_STAT_IDX][i]); + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_read_regfile_acesses[CURRENT_STAT_IDX][i]); else total_inst += - (pwr_core_stat->m_read_regfile_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_read_regfile_acesses[PREV_STAT_IDX][i]); + (pwr_core_stat->m_read_regfile_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_read_regfile_acesses[PREV_STAT_IDX][i]); } return total_inst; } double get_regfile_writes(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) + if (aggregate_stat) total_inst += - (pwr_core_stat->m_write_regfile_acesses[CURRENT_STAT_IDX][i]); + (pwr_core_stat->m_write_regfile_acesses[CURRENT_STAT_IDX][i]); else total_inst += - (pwr_core_stat->m_write_regfile_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_write_regfile_acesses[PREV_STAT_IDX][i]); + (pwr_core_stat->m_write_regfile_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_write_regfile_acesses[PREV_STAT_IDX][i]); } return total_inst; } @@ -337,11 +341,11 @@ class power_stat_t { double get_non_regfile_operands(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += (pwr_core_stat->m_non_rf_operands[CURRENT_STAT_IDX][i]); + if (aggregate_stat) + total_inst += (pwr_core_stat->m_non_rf_operands[CURRENT_STAT_IDX][i]); else total_inst += (pwr_core_stat->m_non_rf_operands[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_non_rf_operands[PREV_STAT_IDX][i]); + (pwr_core_stat->m_non_rf_operands[PREV_STAT_IDX][i]); } return total_inst; } @@ -364,45 +368,49 @@ class power_stat_t { return total_inst; } - double get_sqrt_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst+=(pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]); - else - total_inst+=(pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sqrt_acesses[PREV_STAT_IDX][i]); - } - return total_inst; + double get_sqrt_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sqrt_acesses[PREV_STAT_IDX][i]); + } + return total_inst; } - double get_log_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst+=(pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]); - else - total_inst+=(pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_log_acesses[PREV_STAT_IDX][i]); - } - return total_inst; + double get_log_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_log_acesses[PREV_STAT_IDX][i]); + } + return total_inst; } - double get_sin_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst+=(pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]); - else - total_inst+=(pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_sin_acesses[PREV_STAT_IDX][i]); - } - return total_inst; + double get_sin_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sin_acesses[PREV_STAT_IDX][i]); + } + return total_inst; } - double get_exp_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst+=(pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]); - else - total_inst+=(pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_exp_acesses[PREV_STAT_IDX][i]); - } - return total_inst; + double get_exp_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_exp_acesses[PREV_STAT_IDX][i]); + } + return total_inst; } double get_mem_accessess() { @@ -417,11 +425,11 @@ class power_stat_t { double get_intdiv_accessess(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]); else total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_idiv_acesses[PREV_STAT_IDX][i]); + (pwr_core_stat->m_num_idiv_acesses[PREV_STAT_IDX][i]); } return total_inst; } @@ -429,11 +437,12 @@ class power_stat_t { double get_fpdiv_accessess(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]); } return total_inst; } @@ -441,11 +450,13 @@ class power_stat_t { double get_intmul32_accessess(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]); + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]); } return total_inst; } @@ -453,118 +464,126 @@ class power_stat_t { double get_intmul24_accessess(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]); + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_intmul_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst+= (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]); - else - total_inst+= (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]); - } - return total_inst; + double get_intmul_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]); + } + return total_inst; } - double get_fpmul_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]); + double get_fpmul_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_fp_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - + double get_fp_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_fp_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_dp_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]) - + double get_dp_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_dp_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_dpmul_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) + double get_dpmul_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_dpmul_acesses[PREV_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpmul_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_dpdiv_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) + double get_dpdiv_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_dpdiv_acesses[PREV_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpdiv_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_tensor_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_tensor_core_acesses[PREV_STAT_IDX][i]); + double get_tensor_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tensor_core_acesses[PREV_STAT_IDX][i]); } return total_inst; } - double get_const_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += pwr_core_stat->m_num_const_acesses[CURRENT_STAT_IDX][i]; - else - total_inst += (pwr_core_stat->m_num_const_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_const_acesses[PREV_STAT_IDX][i]); + double get_const_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += pwr_core_stat->m_num_const_acesses[CURRENT_STAT_IDX][i]; + else + total_inst += + (pwr_core_stat->m_num_const_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_const_acesses[PREV_STAT_IDX][i]); } return (total_inst); } - double get_tex_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) + double get_tex_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]) - + else + total_inst += (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]) - (pwr_core_stat->m_num_tex_acesses[PREV_STAT_IDX][i]); } return total_inst; @@ -590,23 +609,24 @@ class power_stat_t { m_config->gpgpu_num_sfu_units; } - float get_active_threads(bool aggregate_stat) { unsigned total_threads = 0; unsigned total_warps = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat){ - total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) ; + if (aggregate_stat) { + total_threads += + (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]); total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]); + } else { + total_threads += + (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_threads[PREV_STAT_IDX][i]); + total_warps += + (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_warps[PREV_STAT_IDX][i]); } - else{ - total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_active_exu_threads[PREV_STAT_IDX][i]); - total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_active_exu_warps[PREV_STAT_IDX][i]); - } } - if(total_warps != 0) + if (total_warps != 0) return (float)((float)total_threads / (float)total_warps); else return 0; @@ -615,98 +635,98 @@ class power_stat_t { unsigned long long get_tot_threads_kernel(bool aggregate_stat) { unsigned total_threads = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat){ - total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) ; + if (aggregate_stat) { + total_threads += + (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]); + } else { + total_threads += + (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_threads[PREV_STAT_IDX][i]); } - else{ - total_threads += (pwr_core_stat->m_active_exu_threads[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_active_exu_threads[PREV_STAT_IDX][i]); - } } - return total_threads; + return total_threads; } unsigned long long get_tot_warps_kernel(bool aggregate_stat) { unsigned long long total_warps = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat){ + if (aggregate_stat) { total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]); + } else { + total_warps += + (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_active_exu_warps[PREV_STAT_IDX][i]); } - else{ - total_warps += (pwr_core_stat->m_active_exu_warps[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_active_exu_warps[PREV_STAT_IDX][i]); - } } - return total_warps; + return total_warps; } - - double get_tot_fpu_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]); + double get_tot_fpu_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]); else - total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fp_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_dp_acesses[PREV_STAT_IDX][i]); + total_inst += (pwr_core_stat->m_num_fp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fp_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_dp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dp_acesses[PREV_STAT_IDX][i]); } - //total_inst += get_total_load_inst()+get_total_store_inst()+get_tex_inst(); + // total_inst += + // get_total_load_inst()+get_total_store_inst()+get_tex_inst(); return total_inst; } - - - double get_tot_sfu_accessess(bool aggregate_stat){ - double total_inst=0; - for(unsigned i=0; i<m_config->num_shader();i++){ - if(aggregate_stat) - total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i])+ - (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]); - else - total_inst += (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_idiv_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_sqrt_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_log_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_sin_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_exp_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_dpmul_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_dpdiv_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_tensor_core_acesses[PREV_STAT_IDX][i]) + - (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_tex_acesses[PREV_STAT_IDX][i]); - + double get_tot_sfu_accessess(bool aggregate_stat) { + double total_inst = 0; + for (unsigned i = 0; i < m_config->num_shader(); i++) { + if (aggregate_stat) + total_inst += + (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) + + (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]); + else + total_inst += + (pwr_core_stat->m_num_idiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_idiv_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul32_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul32_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_sqrt_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sqrt_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_log_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_log_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_sin_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_sin_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_exp_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_exp_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_fpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpdiv_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_fpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_fpmul_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_dpmul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpmul_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_dpdiv_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_dpdiv_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul24_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul24_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_imul_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_imul_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_tensor_core_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tensor_core_acesses[PREV_STAT_IDX][i]) + + (pwr_core_stat->m_num_tex_acesses[CURRENT_STAT_IDX][i]) - + (pwr_core_stat->m_num_tex_acesses[PREV_STAT_IDX][i]); } return total_inst; } @@ -714,11 +734,11 @@ class power_stat_t { double get_ialu_accessess(bool aggregate_stat) { double total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) + if (aggregate_stat) total_inst += (pwr_core_stat->m_num_ialu_acesses[CURRENT_STAT_IDX][i]); - else + else total_inst += (pwr_core_stat->m_num_ialu_acesses[CURRENT_STAT_IDX][i]) - - (pwr_core_stat->m_num_ialu_acesses[PREV_STAT_IDX][i]); + (pwr_core_stat->m_num_ialu_acesses[PREV_STAT_IDX][i]); } return total_inst; } @@ -805,17 +825,16 @@ class power_stat_t { sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat) + if (aggregate_stat) return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, num_request_status)); else return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); } double get_inst_c_misses(bool aggregate_stat) { enum mem_access_type access_type[] = {INST_ACC_R}; @@ -824,46 +843,45 @@ class power_stat_t { sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat) + if (aggregate_stat) return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, num_request_status)); else return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); } double get_inst_c_hits(bool aggregate_stat) { - return (get_inst_c_accesses(aggregate_stat) - get_inst_c_misses(aggregate_stat)); + return (get_inst_c_accesses(aggregate_stat) - + get_inst_c_misses(aggregate_stat)); } double get_l1d_read_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_R, LOCAL_ACC_R}; - enum cache_request_status request_status[] = {HIT, MISS, SECTOR_MISS}; + enum cache_request_status request_status[] = {HIT, MISS, SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ + if (aggregate_stat) { return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + access_type, num_access_type, request_status, num_request_status)); + } else { return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } } double get_l1d_read_misses(bool aggregate_stat) { - return (get_l1d_read_accesses(aggregate_stat) - get_l1d_read_hits(aggregate_stat)); + return (get_l1d_read_accesses(aggregate_stat) - + get_l1d_read_hits(aggregate_stat)); } double get_l1d_read_hits(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_R, LOCAL_ACC_R}; @@ -873,19 +891,17 @@ class power_stat_t { unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + if (aggregate_stat) { return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } + access_type, num_access_type, request_status, num_request_status)); + } else { + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } } double get_l1d_write_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W}; @@ -895,22 +911,21 @@ class power_stat_t { unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + if (aggregate_stat) { return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } + access_type, num_access_type, request_status, num_request_status)); + } else { + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } } double get_l1d_write_misses(bool aggregate_stat) { - return (get_l1d_write_accesses(aggregate_stat) - get_l1d_write_hits(aggregate_stat)); + return (get_l1d_write_accesses(aggregate_stat) - + get_l1d_write_hits(aggregate_stat)); } double get_l1d_write_hits(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W}; @@ -920,19 +935,17 @@ class power_stat_t { unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ - return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + if (aggregate_stat) { return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } + access_type, num_access_type, request_status, num_request_status)); + } else { + return (pwr_mem_stat->core_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->core_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); + } } double get_cache_misses() { return get_l1d_read_misses(0) + get_constant_c_misses() + @@ -949,111 +962,107 @@ class power_stat_t { double get_shmem_access(bool aggregate_stat) { unsigned total_inst = 0; for (unsigned i = 0; i < m_config->num_shader(); i++) { - if(aggregate_stat) + if (aggregate_stat) total_inst += (pwr_mem_stat->shmem_access[CURRENT_STAT_IDX][i]); else total_inst += (pwr_mem_stat->shmem_access[CURRENT_STAT_IDX][i]) - - (pwr_mem_stat->shmem_access[PREV_STAT_IDX][i]); + (pwr_mem_stat->shmem_access[PREV_STAT_IDX][i]); } return total_inst; } - unsigned long long get_l2_read_accesses(bool aggregate_stat) { + unsigned long long get_l2_read_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = { GLOBAL_ACC_R, LOCAL_ACC_R, CONST_ACC_R, TEXTURE_ACC_R, INST_ACC_R}; - enum cache_request_status request_status[] = {HIT, HIT_RESERVED, MISS, SECTOR_MISS}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED, MISS, + SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ - return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + if (aggregate_stat) { return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, num_request_status)); + } else { + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); } } unsigned long long get_l2_read_misses(bool aggregate_stat) { - return (get_l2_read_accesses(aggregate_stat) - get_l2_read_hits(aggregate_stat)); + return (get_l2_read_accesses(aggregate_stat) - + get_l2_read_hits(aggregate_stat)); } unsigned long long get_l2_read_hits(bool aggregate_stat) { - enum mem_access_type access_type[] = { + enum mem_access_type access_type[] = { GLOBAL_ACC_R, LOCAL_ACC_R, CONST_ACC_R, TEXTURE_ACC_R, INST_ACC_R}; - enum cache_request_status request_status[] = {HIT, HIT_RESERVED}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ - return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + if (aggregate_stat) { return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, num_request_status)); + } else { + return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); } } unsigned long long get_l2_write_accesses(bool aggregate_stat) { enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W, L1_WRBK_ACC}; - enum cache_request_status request_status[] = {HIT, HIT_RESERVED, MISS, SECTOR_MISS}; + enum cache_request_status request_status[] = {HIT, HIT_RESERVED, MISS, + SECTOR_MISS}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ + if (aggregate_stat) { return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + access_type, num_access_type, request_status, num_request_status)); + } else { return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); } } unsigned long long get_l2_write_misses(bool aggregate_stat) { - return (get_l2_write_accesses(aggregate_stat) - get_l2_write_hits(aggregate_stat)); + return (get_l2_write_accesses(aggregate_stat) - + get_l2_write_hits(aggregate_stat)); } unsigned long long get_l2_write_hits(bool aggregate_stat) { - enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W, + enum mem_access_type access_type[] = {GLOBAL_ACC_W, LOCAL_ACC_W, L1_WRBK_ACC}; enum cache_request_status request_status[] = {HIT, HIT_RESERVED}; unsigned num_access_type = sizeof(access_type) / sizeof(enum mem_access_type); unsigned num_request_status = sizeof(request_status) / sizeof(enum cache_request_status); - if(aggregate_stat){ + if (aggregate_stat) { return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); - } - else{ + access_type, num_access_type, request_status, num_request_status)); + } else { return (pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)) - - (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( - access_type, num_access_type, request_status, - num_request_status)); + access_type, num_access_type, request_status, + num_request_status)) - + (pwr_mem_stat->l2_cache_stats[PREV_STAT_IDX].get_stats( + access_type, num_access_type, request_status, + num_request_status)); } } double get_dram_cmd() { @@ -1091,12 +1100,11 @@ class power_stat_t { double get_dram_pre(bool aggregate_stat) { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { - if(aggregate_stat){ + if (aggregate_stat) { total += pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i]; - } - else{ + } else { total += (pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_pre[PREV_STAT_IDX][i]); + pwr_mem_stat->n_pre[PREV_STAT_IDX][i]); } } return total; @@ -1104,12 +1112,11 @@ class power_stat_t { double get_dram_rd(bool aggregate_stat) { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { - if(aggregate_stat){ + if (aggregate_stat) { total += pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i]; - } - else{ + } else { total += (pwr_mem_stat->n_rd[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_rd[PREV_STAT_IDX][i]); + pwr_mem_stat->n_rd[PREV_STAT_IDX][i]); } } return total; @@ -1117,15 +1124,14 @@ class power_stat_t { double get_dram_wr(bool aggregate_stat) { unsigned total = 0; for (unsigned i = 0; i < m_mem_config->m_n_mem; ++i) { - if(aggregate_stat){ - total += pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] + - pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i]; - } - else{ - total += (pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_wr[PREV_STAT_IDX][i]) + - (pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_wr_WB[PREV_STAT_IDX][i]); + if (aggregate_stat) { + total += pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] + + pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i]; + } else { + total += (pwr_mem_stat->n_wr[CURRENT_STAT_IDX][i] - + pwr_mem_stat->n_wr[PREV_STAT_IDX][i]) + + (pwr_mem_stat->n_wr_WB[CURRENT_STAT_IDX][i] - + pwr_mem_stat->n_wr_WB[PREV_STAT_IDX][i]); } } return total; @@ -1141,13 +1147,12 @@ class power_stat_t { unsigned long long get_icnt_simt_to_mem(bool aggregate_stat) { long total = 0; - for (unsigned i = 0; i < m_config->n_simt_clusters; ++i){ - if(aggregate_stat){ + for (unsigned i = 0; i < m_config->n_simt_clusters; ++i) { + if (aggregate_stat) { total += pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i]; - } - else{ + } else { total += (pwr_mem_stat->n_simt_to_mem[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_simt_to_mem[PREV_STAT_IDX][i]); + pwr_mem_stat->n_simt_to_mem[PREV_STAT_IDX][i]); } } return total; @@ -1156,13 +1161,13 @@ class power_stat_t { unsigned long long get_icnt_mem_to_simt(bool aggregate_stat) { long total = 0; for (unsigned i = 0; i < m_config->n_simt_clusters; ++i) { - if(aggregate_stat){ + if (aggregate_stat) { total += pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i]; } - - else{ + + else { total += (pwr_mem_stat->n_mem_to_simt[CURRENT_STAT_IDX][i] - - pwr_mem_stat->n_mem_to_simt[PREV_STAT_IDX][i]); + pwr_mem_stat->n_mem_to_simt[PREV_STAT_IDX][i]); } } return total; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 855aa1c..9fe4c09 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas, -// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos +// Hardavellas, Mahmoud Khairy, Junrui Pan, Timothy G. Rogers The University of +// British Columbia, Northwestern University, Purdue University All rights +// reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -187,20 +188,16 @@ void shader_core_ctx::create_schedulers() { // must currently occur after all inputs have been initialized. std::string sched_config = m_config->gpgpu_scheduler_string; const concrete_scheduler scheduler = - sched_config.find("lrr") != std::string::npos - ? CONCRETE_SCHEDULER_LRR - : sched_config.find("two_level_active") != std::string::npos - ? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE - : sched_config.find("gto") != std::string::npos - ? CONCRETE_SCHEDULER_GTO - : sched_config.find("rrr") != std::string::npos - ? CONCRETE_SCHEDULER_RRR - : sched_config.find("old") != std::string::npos - ? CONCRETE_SCHEDULER_OLDEST_FIRST - : sched_config.find("warp_limiting") != - std::string::npos - ? CONCRETE_SCHEDULER_WARP_LIMITING - : NUM_CONCRETE_SCHEDULERS; + sched_config.find("lrr") != std::string::npos ? CONCRETE_SCHEDULER_LRR + : sched_config.find("two_level_active") != std::string::npos + ? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE + : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO + : sched_config.find("rrr") != std::string::npos ? CONCRETE_SCHEDULER_RRR + : sched_config.find("old") != std::string::npos + ? CONCRETE_SCHEDULER_OLDEST_FIRST + : sched_config.find("warp_limiting") != std::string::npos + ? CONCRETE_SCHEDULER_WARP_LIMITING + : NUM_CONCRETE_SCHEDULERS; assert(scheduler != NUM_CONCRETE_SCHEDULERS); for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) { @@ -487,8 +484,8 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_sid = shader_id; m_tpc = tpc_id; - if(get_gpu()->get_config().g_power_simulation_enabled){ - scaling_coeffs = get_gpu()->get_scaling_coeffs(); + if (get_gpu()->get_config().g_power_simulation_enabled) { + scaling_coeffs = get_gpu()->get_scaling_coeffs(); } m_last_inst_gpu_sim_cycle = 0; @@ -641,7 +638,8 @@ void shader_core_stats::print(FILE *fout) const { fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn); fprintf(fout, "gpgpu_n_shmem_bkconflict = %d\n", gpgpu_n_shmem_bkconflict); - fprintf(fout, "gpgpu_n_l1cache_bkconflict = %d\n", gpgpu_n_l1cache_bkconflict); + fprintf(fout, "gpgpu_n_l1cache_bkconflict = %d\n", + gpgpu_n_l1cache_bkconflict); fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge); @@ -893,7 +891,9 @@ void shader_core_ctx::decode() { m_warp[m_inst_fetch_buffer.m_warp_id]->inc_inst_in_pipeline(); if (pI1) { m_stats->m_num_decoded_insn[m_sid]++; - if ((pI1->oprnd_type == INT_OP) || (pI1->oprnd_type == UN_OP)) { //these counters get added up in mcPat to compute scheduler power + if ((pI1->oprnd_type == INT_OP) || + (pI1->oprnd_type == UN_OP)) { // these counters get added up in mcPat + // to compute scheduler power m_stats->m_num_INTdecoded_insn[m_sid]++; } else if (pI1->oprnd_type == FP_OP) { m_stats->m_num_FPdecoded_insn[m_sid]++; @@ -904,7 +904,9 @@ void shader_core_ctx::decode() { m_warp[m_inst_fetch_buffer.m_warp_id]->ibuffer_fill(1, pI2); m_warp[m_inst_fetch_buffer.m_warp_id]->inc_inst_in_pipeline(); m_stats->m_num_decoded_insn[m_sid]++; - if ((pI1->oprnd_type == INT_OP) || (pI1->oprnd_type == UN_OP)) { //these counters get added up in mcPat to compute scheduler power + if ((pI1->oprnd_type == INT_OP) || + (pI1->oprnd_type == UN_OP)) { // these counters get added up in + // mcPat to compute scheduler power m_stats->m_num_INTdecoded_insn[m_sid]++; } else if (pI2->oprnd_type == FP_OP) { m_stats->m_num_FPdecoded_insn[m_sid]++; @@ -950,7 +952,8 @@ void shader_core_ctx::fetch() { m_threadState[tid].m_active = false; unsigned cta_id = m_warp[warp_id]->get_cta_id(); if (m_thread[tid] == NULL) { - register_cta_thread_exit(cta_id, m_warp[warp_id]->get_kernel_info()); + register_cta_thread_exit(cta_id, + m_warp[warp_id]->get_kernel_info()); } else { register_cta_thread_exit(cta_id, &(m_thread[tid]->get_kernel())); @@ -987,11 +990,10 @@ void shader_core_ctx::fetch() { m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); std::list<cache_event> events; enum cache_request_status status; - if (m_config->perfect_inst_const_cache){ + if (m_config->perfect_inst_const_cache) { status = HIT; shader_cache_access_log(m_sid, INSTRUCTION, 0); - } - else + } else status = m_L1I->access( (new_addr_type)ppc, mf, m_gpu->gpu_sim_cycle + m_gpu->gpu_tot_sim_cycle, events); @@ -1050,14 +1052,13 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set, if (next_inst->m_is_ldgsts) { if (m_warp[warp_id]->m_ldgdepbar_buf.size() == ldgdepbar_id + 1) { m_warp[warp_id]->m_ldgdepbar_buf[ldgdepbar_id].push_back(*next_inst); - } - else { + } else { assert(m_warp[warp_id]->m_ldgdepbar_buf.size() < ldgdepbar_id + 1); std::vector<warp_inst_t> l; l.push_back(*next_inst); m_warp[warp_id]->m_ldgdepbar_buf.push_back(l); } - // If the mask of the instruction is all 0, then the address is also 0, + // If the mask of the instruction is all 0, then the address is also 0, // so that there's no need to check through the writeback if (next_inst->get_active_mask() == 0) { (m_warp[warp_id]->m_ldgdepbar_buf.back()).back().pc = -1; @@ -1071,7 +1072,7 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set, } else if (next_inst->op == MEMORY_BARRIER_OP) { m_warp[warp_id]->set_membar(); - } else if (next_inst->m_is_ldgdepbar) { // Add for LDGDEPBAR + } else if (next_inst->m_is_ldgdepbar) { // Add for LDGDEPBAR m_warp[warp_id]->m_ldgdepbar_id++; // If there are no added LDGSTS, insert an empty vector if (m_warp[warp_id]->m_ldgdepbar_buf.size() != ldgdepbar_id + 1) { @@ -1082,16 +1083,20 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set, } else if (next_inst->m_is_depbar) { // Add for DEPBAR // Set to true immediately when a DEPBAR instruction is met m_warp[warp_id]->m_waiting_ldgsts = true; - m_warp[warp_id]->m_depbar_group = next_inst->m_depbar_group_no; // set in trace_driven.cc + m_warp[warp_id]->m_depbar_group = + next_inst->m_depbar_group_no; // set in trace_driven.cc - // Record the last group that's possbily being monitored by this DEPBAR instr + // Record the last group that's possbily being monitored by this DEPBAR + // instr m_warp[warp_id]->m_depbar_start_id = m_warp[warp_id]->m_ldgdepbar_id - 1; - - // Record the last group that's actually being monitored by this DEPBAR instr - unsigned int end_group = m_warp[warp_id]->m_ldgdepbar_id - m_warp[warp_id]->m_depbar_group; - // Check for the case that the LDGSTSs monitored have finished when encountering the - // DEPBAR instruction + // Record the last group that's actually being monitored by this DEPBAR + // instr + unsigned int end_group = + m_warp[warp_id]->m_ldgdepbar_id - m_warp[warp_id]->m_depbar_group; + + // Check for the case that the LDGSTSs monitored have finished when + // encountering the DEPBAR instruction bool done_flag = true; for (int i = 0; i < end_group; i++) { for (int j = 0; j < m_warp[warp_id]->m_ldgdepbar_buf[i].size(); j++) { @@ -1101,7 +1106,7 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set, } } } - + UpdateDEPBAR: if (done_flag) { if (m_warp[warp_id]->m_waiting_ldgsts) { @@ -1184,11 +1189,12 @@ void scheduler_unit::order_rrr( if (m_num_issued_last_cycle > 0 || warp(m_current_turn_warp).done_exit() || warp(m_current_turn_warp).waiting()) { std::vector<shd_warp_t *>::const_iterator iter = - (last_issued_from_input == input_list.end()) ? - input_list.begin() : last_issued_from_input + 1; + (last_issued_from_input == input_list.end()) + ? input_list.begin() + : last_issued_from_input + 1; for (unsigned count = 0; count < num_warps_to_add; ++iter, ++count) { if (iter == input_list.end()) { - iter = input_list.begin(); + iter = input_list.begin(); } unsigned warp_id = (*iter)->get_warp_id(); if (!(*iter)->done_exit() && !(*iter)->waiting()) { @@ -1854,33 +1860,38 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const { // Add this function to unset depbar void shader_core_ctx::unset_depbar(const warp_inst_t &inst) { bool done_flag = true; - unsigned int end_group = m_warp[inst.warp_id()]->m_depbar_start_id == 0 ? - m_warp[inst.warp_id()]->m_ldgdepbar_buf.size() : - (m_warp[inst.warp_id()]->m_depbar_start_id - m_warp[inst.warp_id()]->m_depbar_group + 1); + unsigned int end_group = m_warp[inst.warp_id()]->m_depbar_start_id == 0 + ? m_warp[inst.warp_id()]->m_ldgdepbar_buf.size() + : (m_warp[inst.warp_id()]->m_depbar_start_id - + m_warp[inst.warp_id()]->m_depbar_group + 1); - if (inst.m_is_ldgsts) { + if (inst.m_is_ldgsts) { for (int i = 0; i < m_warp[inst.warp_id()]->m_ldgdepbar_buf.size(); i++) { - for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); j++) { + for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); + j++) { if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc == inst.pc) { - // Handle the case that same pc results in multiple LDGSTS instructions - if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].get_addr(0) == inst.get_addr(0)) { + // Handle the case that same pc results in multiple LDGSTS + // instructions + if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].get_addr(0) == + inst.get_addr(0)) { m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc = -1; goto DoneWB; } - } + } } } DoneWB: for (int i = 0; i < end_group; i++) { - for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); j++) { + for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); + j++) { if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc != -1) { done_flag = false; goto UpdateDEPBAR; } } } - + UpdateDEPBAR: if (done_flag) { if (m_warp[inst.warp_id()]->m_waiting_ldgsts) { @@ -2000,7 +2011,7 @@ mem_stage_stall_type ldst_unit::process_cache_access( if (inst.is_load()) { for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]]--; - + // release LDGSTS if (inst.m_is_ldgsts) { m_pending_ldgsts[inst.warp_id()][inst.pc][inst.get_addr(0)]--; @@ -2139,8 +2150,12 @@ void ldst_unit::L1_latency_queue_cycle() { // release LDGSTS if (mf_next->get_inst().m_is_ldgsts) { - m_pending_ldgsts[mf_next->get_inst().warp_id()][mf_next->get_inst().pc][mf_next->get_inst().get_addr(0)]--; - if (m_pending_ldgsts[mf_next->get_inst().warp_id()][mf_next->get_inst().pc][mf_next->get_inst().get_addr(0)] == 0) { + m_pending_ldgsts[mf_next->get_inst().warp_id()] + [mf_next->get_inst().pc] + [mf_next->get_inst().get_addr(0)]--; + if (m_pending_ldgsts[mf_next->get_inst().warp_id()] + [mf_next->get_inst().pc] + [mf_next->get_inst().get_addr(0)] == 0) { m_core->unset_depbar(mf_next->get_inst()); } } @@ -2207,7 +2222,8 @@ bool ldst_unit::constant_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail, while (inst.accessq_count() > 0) inst.accessq_pop_back(); if (inst.is_load()) { for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) - if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]] -= access_count; + if (inst.out[r] > 0) + m_pending_writes[inst.warp_id()][inst.out[r]] -= access_count; } } else { fail = process_memory_access_queue(m_L1C, inst); @@ -2395,7 +2411,7 @@ void sp_unit::active_lanes_in_pipeline() { void dp_unit::active_lanes_in_pipeline() { unsigned active_count = pipelined_simd_unit::get_active_lanes_in_pipeline(); assert(active_count <= m_core->get_config()->warp_size); - //m_core->incspactivelanes_stat(active_count); + // m_core->incspactivelanes_stat(active_count); m_core->incfuactivelanes_stat(active_count); m_core->incfumemactivelanes_stat(active_count); } @@ -2527,9 +2543,9 @@ void pipelined_simd_unit::cycle() { if (!m_dispatch_reg->dispatch_delay()) { int start_stage = m_dispatch_reg->latency - m_dispatch_reg->initiation_interval; - if(m_pipeline_reg[start_stage]->empty()) { - move_warp(m_pipeline_reg[start_stage], m_dispatch_reg); - active_insts_in_pipeline++; + if (m_pipeline_reg[start_stage]->empty()) { + move_warp(m_pipeline_reg[start_stage], m_dispatch_reg); + active_insts_in_pipeline++; } } } @@ -2682,10 +2698,12 @@ void ldst_unit::writeback() { m_next_wb.out[r]); insn_completed = true; } - } - else if (m_next_wb.m_is_ldgsts) { // for LDGSTS instructions where no output register is used - m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc][m_next_wb.get_addr(0)]--; - if (m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc][m_next_wb.get_addr(0)] == 0) { + } else if (m_next_wb.m_is_ldgsts) { // for LDGSTS instructions where no + // output register is used + m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc] + [m_next_wb.get_addr(0)]--; + if (m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc] + [m_next_wb.get_addr(0)] == 0) { insn_completed = true; } break; @@ -2923,7 +2941,8 @@ void ldst_unit::cycle() { // release LDGSTS if (m_dispatch_reg->m_is_ldgsts) { // m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc][m_dispatch_reg->get_addr(0)]--; - if (m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc][m_dispatch_reg->get_addr(0)] == 0) { + if (m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc] + [m_dispatch_reg->get_addr(0)] == 0) { m_core->unset_depbar(*m_dispatch_reg); } } @@ -3223,68 +3242,68 @@ void warp_inst_t::print(FILE *fout) const { m_config->gpgpu_ctx->func_sim->ptx_print_insn(pc, fout); fprintf(fout, "\n"); } -void shader_core_ctx::incexecstat(warp_inst_t *&inst) -{ - // Latency numbers for next operations are used to scale the power values - // for special operations, according observations from microbenchmarking - // TODO: put these numbers in the xml configuration - if(get_gpu()->get_config().g_power_simulation_enabled){ - switch(inst->sp_op){ - case INT__OP: - incialu_stat(inst->active_count(), scaling_coeffs->int_coeff); - break; - case INT_MUL_OP: - incimul_stat(inst->active_count(), scaling_coeffs->int_mul_coeff); - break; - case INT_MUL24_OP: - incimul24_stat(inst->active_count(), scaling_coeffs->int_mul24_coeff); - break; - case INT_MUL32_OP: - incimul32_stat(inst->active_count(), scaling_coeffs->int_mul32_coeff); - break; - case INT_DIV_OP: - incidiv_stat(inst->active_count(), scaling_coeffs->int_div_coeff); - break; - case FP__OP: - incfpalu_stat(inst->active_count(),scaling_coeffs->fp_coeff); - break; - case FP_MUL_OP: - incfpmul_stat(inst->active_count(), scaling_coeffs->fp_mul_coeff); - break; - case FP_DIV_OP: - incfpdiv_stat(inst->active_count(), scaling_coeffs->fp_div_coeff); - break; - case DP___OP: - incdpalu_stat(inst->active_count(), scaling_coeffs->dp_coeff); - break; - case DP_MUL_OP: - incdpmul_stat(inst->active_count(), scaling_coeffs->dp_mul_coeff); - break; - case DP_DIV_OP: - incdpdiv_stat(inst->active_count(), scaling_coeffs->dp_div_coeff); - break; - case FP_SQRT_OP: - incsqrt_stat(inst->active_count(), scaling_coeffs->sqrt_coeff); - break; - case FP_LG_OP: - inclog_stat(inst->active_count(), scaling_coeffs->log_coeff); - break; - case FP_SIN_OP: - incsin_stat(inst->active_count(), scaling_coeffs->sin_coeff); - break; - case FP_EXP_OP: - incexp_stat(inst->active_count(), scaling_coeffs->exp_coeff); - break; - case TENSOR__OP: - inctensor_stat(inst->active_count(), scaling_coeffs->tensor_coeff); - break; - case TEX__OP: - inctex_stat(inst->active_count(), scaling_coeffs->tex_coeff); - break; - default: - break; +void shader_core_ctx::incexecstat(warp_inst_t *&inst) { + // Latency numbers for next operations are used to scale the power values + // for special operations, according observations from microbenchmarking + // TODO: put these numbers in the xml configuration + if (get_gpu()->get_config().g_power_simulation_enabled) { + switch (inst->sp_op) { + case INT__OP: + incialu_stat(inst->active_count(), scaling_coeffs->int_coeff); + break; + case INT_MUL_OP: + incimul_stat(inst->active_count(), scaling_coeffs->int_mul_coeff); + break; + case INT_MUL24_OP: + incimul24_stat(inst->active_count(), scaling_coeffs->int_mul24_coeff); + break; + case INT_MUL32_OP: + incimul32_stat(inst->active_count(), scaling_coeffs->int_mul32_coeff); + break; + case INT_DIV_OP: + incidiv_stat(inst->active_count(), scaling_coeffs->int_div_coeff); + break; + case FP__OP: + incfpalu_stat(inst->active_count(), scaling_coeffs->fp_coeff); + break; + case FP_MUL_OP: + incfpmul_stat(inst->active_count(), scaling_coeffs->fp_mul_coeff); + break; + case FP_DIV_OP: + incfpdiv_stat(inst->active_count(), scaling_coeffs->fp_div_coeff); + break; + case DP___OP: + incdpalu_stat(inst->active_count(), scaling_coeffs->dp_coeff); + break; + case DP_MUL_OP: + incdpmul_stat(inst->active_count(), scaling_coeffs->dp_mul_coeff); + break; + case DP_DIV_OP: + incdpdiv_stat(inst->active_count(), scaling_coeffs->dp_div_coeff); + break; + case FP_SQRT_OP: + incsqrt_stat(inst->active_count(), scaling_coeffs->sqrt_coeff); + break; + case FP_LG_OP: + inclog_stat(inst->active_count(), scaling_coeffs->log_coeff); + break; + case FP_SIN_OP: + incsin_stat(inst->active_count(), scaling_coeffs->sin_coeff); + break; + case FP_EXP_OP: + incexp_stat(inst->active_count(), scaling_coeffs->exp_coeff); + break; + case TENSOR__OP: + inctensor_stat(inst->active_count(), scaling_coeffs->tensor_coeff); + break; + case TEX__OP: + inctex_stat(inst->active_count(), scaling_coeffs->tex_coeff); + break; + default: + break; } - if(inst->const_cache_operand) //warp has const address space load as one operand + if (inst->const_cache_operand) // warp has const address space load as one + // operand inc_const_accesses(1); } } @@ -4034,7 +4053,9 @@ void shader_core_ctx::get_icnt_power_stats(long &n_simt_to_mem, n_mem_to_simt += m_stats->n_mem_to_simt[m_sid]; } -kernel_info_t* shd_warp_t::get_kernel_info() const { return m_shader->get_kernel_info(); } +kernel_info_t *shd_warp_t::get_kernel_info() const { + return m_shader->get_kernel_info(); +} bool shd_warp_t::functional_done() const { return get_n_completed() == m_warp_size; @@ -4069,7 +4090,8 @@ bool shd_warp_t::waiting() { void shd_warp_t::print(FILE *fout) const { if (!done_exit()) { - fprintf(fout, "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ", + fprintf(fout, + "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ", m_warp_id, m_next_pc, (functional_done() ? 'f' : ' '), (stores_done() ? 's' : ' '), (inst_in_pipeline() ? ' ' : 'i'), (done_exit() ? 'e' : ' '), n_completed, m_inst_in_pipeline, @@ -4156,18 +4178,18 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) { unsigned cusPerSched = m_cu.size() / m_num_warp_scheds; reg_id = j / cusPerSched; } - m_cu[j]->init(j, num_banks, shader->get_config(), this, - sub_core_model, reg_id, m_num_banks_per_sched); + m_cu[j]->init(j, num_banks, shader->get_config(), this, sub_core_model, + reg_id, m_num_banks_per_sched); } for (unsigned j = 0; j < m_dispatch_units.size(); j++) { - m_dispatch_units[j].init(sub_core_model,m_num_warp_scheds); + m_dispatch_units[j].init(sub_core_model, m_num_warp_scheds); } m_initialized = true; } unsigned register_bank(int regnum, int wid, unsigned num_banks, - bool sub_core_model, - unsigned banks_per_sched, unsigned sched_id) { + bool sub_core_model, unsigned banks_per_sched, + unsigned sched_id) { int bank = regnum; bank += wid; if (sub_core_model) { @@ -4186,14 +4208,13 @@ bool opndcoll_rfu_t::writeback(warp_inst_t &inst) { int reg_num = inst.arch_reg.dst[op]; // this math needs to match that used // in function_info::ptx_decode_inst if (reg_num >= 0) { // valid register - unsigned bank = register_bank(reg_num, inst.warp_id(), m_num_banks, - sub_core_model, - m_num_banks_per_sched, inst.get_schd_id()); + unsigned bank = + register_bank(reg_num, inst.warp_id(), m_num_banks, sub_core_model, + m_num_banks_per_sched, inst.get_schd_id()); if (m_arbiter.bank_idle(bank)) { m_arbiter.allocate_bank_for_write( - bank, - op_t(&inst, reg_num, m_num_banks, sub_core_model, - m_num_banks_per_sched, inst.get_schd_id())); + bank, op_t(&inst, reg_num, m_num_banks, sub_core_model, + m_num_banks_per_sched, inst.get_schd_id())); inst.arch_reg.dst[op] = -1; } else { return false; @@ -4301,9 +4322,8 @@ void opndcoll_rfu_t::allocate_reads() { const op_t &rr = *r; unsigned reg = rr.get_reg(); unsigned wid = rr.get_wid(); - unsigned bank = - register_bank(reg, wid, m_num_banks, sub_core_model, - m_num_banks_per_sched, rr.get_sid()); + unsigned bank = register_bank(reg, wid, m_num_banks, sub_core_model, + m_num_banks_per_sched, rr.get_sid()); m_arbiter.allocate_for_read(bank, rr); read_ops[bank] = rr; } @@ -4353,10 +4373,12 @@ void opndcoll_rfu_t::collector_unit_t::dump( } } -void opndcoll_rfu_t::collector_unit_t::init( - unsigned n, unsigned num_banks, - const core_config *config, opndcoll_rfu_t *rfu, bool sub_core_model, - unsigned reg_id, unsigned banks_per_sched) { +void opndcoll_rfu_t::collector_unit_t::init(unsigned n, unsigned num_banks, + const core_config *config, + opndcoll_rfu_t *rfu, + bool sub_core_model, + unsigned reg_id, + unsigned banks_per_sched) { m_rfu = rfu; m_cuid = n; m_num_banks = num_banks; @@ -4376,7 +4398,7 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set, warp_inst_t **pipeline_reg = pipeline_reg_set->get_ready(); if ((pipeline_reg) and !((*pipeline_reg)->empty())) { m_warp_id = (*pipeline_reg)->warp_id(); - std::vector<int> prev_regs; // remove duplicate regs within same instr + std::vector<int> prev_regs; // remove duplicate regs within same instr for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) { int reg_num = (*pipeline_reg) @@ -4384,14 +4406,13 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set, // function_info::ptx_decode_inst bool new_reg = true; for (auto r : prev_regs) { - if (r == reg_num) - new_reg = false; + if (r == reg_num) new_reg = false; } - if (reg_num >= 0 && new_reg) { // valid register + if (reg_num >= 0 && new_reg) { // valid register prev_regs.push_back(reg_num); - m_src_op[op] = op_t(this, op, reg_num, m_num_banks, - m_sub_core_model, m_num_banks_per_sched, - (*pipeline_reg)->get_schd_id()); + m_src_op[op] = + op_t(this, op, reg_num, m_num_banks, m_sub_core_model, + m_num_banks_per_sched, (*pipeline_reg)->get_schd_id()); m_not_ready.set(op); } else m_src_op[op] = op_t(); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 95e142e..b1f904f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1,18 +1,19 @@ // Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Andrew Turner, -// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas, +// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas, // Mahmoud Khairy, Junrui Pan, Timothy G. Rogers -// The University of British Columbia, Northwestern University, Purdue University -// All rights reserved. +// The University of British Columbia, Northwestern University, Purdue +// University All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // -// 1. Redistributions of source code must retain the above copyright notice, this +// 1. Redistributions of source code must retain the above copyright notice, +// this // list of conditions and the following disclaimer; // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution; -// 3. Neither the names of The University of British Columbia, Northwestern +// 3. Neither the names of The University of British Columbia, Northwestern // University nor the names of their contributors may be used to // endorse or promote products derived from this software without specific // prior written permission. @@ -199,7 +200,7 @@ class shd_warp_t { void clear_membar() { m_membar = false; } bool get_membar() const { return m_membar; } virtual address_type get_pc() const { return m_next_pc; } - virtual kernel_info_t* get_kernel_info() const; + virtual kernel_info_t *get_kernel_info() const; void set_next_pc(address_type pc) { m_next_pc = pc; } void store_info_of_last_inst_at_barrier(const warp_inst_t *pI) { @@ -318,12 +319,14 @@ class shd_warp_t { bool m_cdp_dummy; // Ni: LDGDEPBAR barrier support - public: - unsigned int m_ldgdepbar_id; // LDGDEPBAR barrier ID - std::vector<std::vector<warp_inst_t>> m_ldgdepbar_buf; // LDGDEPBAR barrier buffer - unsigned int m_depbar_start_id; - unsigned int m_depbar_group; - bool m_waiting_ldgsts; // Ni: Whether the warp is waiting for the LDGSTS instrs to finish + public: + unsigned int m_ldgdepbar_id; // LDGDEPBAR barrier ID + std::vector<std::vector<warp_inst_t>> + m_ldgdepbar_buf; // LDGDEPBAR barrier buffer + unsigned int m_depbar_start_id; + unsigned int m_depbar_group; + bool m_waiting_ldgsts; // Ni: Whether the warp is waiting for the LDGSTS + // instrs to finish }; inline unsigned hw_tid_from_wid(unsigned wid, unsigned warp_size, unsigned i) { @@ -337,8 +340,8 @@ const unsigned WARP_PER_CTA_MAX = 64; typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t; unsigned register_bank(int regnum, int wid, unsigned num_banks, - bool sub_core_model, - unsigned banks_per_sched, unsigned sched_id); + bool sub_core_model, unsigned banks_per_sched, + unsigned sched_id); class shader_core_ctx; class shader_core_config; @@ -681,28 +684,26 @@ class opndcoll_rfu_t { // operand collector based register file unit public: op_t() { m_valid = false; } op_t(collector_unit_t *cu, unsigned op, unsigned reg, unsigned num_banks, - bool sub_core_model, - unsigned banks_per_sched, unsigned sched_id) { + bool sub_core_model, unsigned banks_per_sched, unsigned sched_id) { m_valid = true; m_warp = NULL; m_cu = cu; m_operand = op; m_register = reg; m_shced_id = sched_id; - m_bank = register_bank(reg, cu->get_warp_id(), num_banks, - sub_core_model, banks_per_sched, sched_id); + m_bank = register_bank(reg, cu->get_warp_id(), num_banks, sub_core_model, + banks_per_sched, sched_id); } op_t(const warp_inst_t *warp, unsigned reg, unsigned num_banks, - bool sub_core_model, - unsigned banks_per_sched, unsigned sched_id) { + bool sub_core_model, unsigned banks_per_sched, unsigned sched_id) { m_valid = true; m_warp = warp; m_register = reg; m_cu = NULL; m_operand = -1; m_shced_id = sched_id; - m_bank = register_bank(reg, warp->warp_id(), num_banks, - sub_core_model, banks_per_sched, sched_id); + m_bank = register_bank(reg, warp->warp_id(), num_banks, sub_core_model, + banks_per_sched, sched_id); } // accessors @@ -950,9 +951,8 @@ class opndcoll_rfu_t { // operand collector based register file unit unsigned get_reg_id() const { return m_reg_id; } // modifiers - void init(unsigned n, unsigned num_banks, - const core_config *config, opndcoll_rfu_t *rfu, - bool m_sub_core_model, unsigned reg_id, + void init(unsigned n, unsigned num_banks, const core_config *config, + opndcoll_rfu_t *rfu, bool m_sub_core_model, unsigned reg_id, unsigned num_banks_per_sched); bool allocate(register_set *pipeline_reg, register_set *output_reg); @@ -996,8 +996,8 @@ class opndcoll_rfu_t { // operand collector based register file unit // With sub-core enabled round robin starts with the next cu assigned to a // different sub-core than the one that dispatched last unsigned cusPerSched = m_num_collectors / m_num_warp_scheds; - unsigned rr_increment = m_sub_core_model ? - cusPerSched - (m_last_cu % cusPerSched) : 1; + unsigned rr_increment = + m_sub_core_model ? cusPerSched - (m_last_cu % cusPerSched) : 1; for (unsigned n = 0; n < m_num_collectors; n++) { unsigned c = (m_last_cu + n + rr_increment) % m_num_collectors; if ((*m_collector_units)[c].ready()) { @@ -1317,8 +1317,8 @@ class sp_unit : public pipelined_simd_unit { class specialized_unit : public pipelined_simd_unit { public: specialized_unit(register_set *result_port, const shader_core_config *config, - shader_core_ctx *core, int supported_op, - char *unit_name, unsigned latency, unsigned issue_reg_id); + shader_core_ctx *core, int supported_op, char *unit_name, + unsigned latency, unsigned issue_reg_id); virtual bool can_issue(const warp_inst_t &inst) const { if (inst.op != m_supported_op) { return false; @@ -1348,13 +1348,14 @@ class ldst_unit : public pipelined_simd_unit { unsigned sid, unsigned tpc); // Add a structure to record the LDGSTS instructions, - // similar to m_pending_writes, but since LDGSTS does not have a output register - // to write to, so a new structure needs to be added - /* A multi-level map: unsigned (warp_id) -> unsigned (pc) -> unsigned (addr) -> unsigned (count) + // similar to m_pending_writes, but since LDGSTS does not have a output + // register to write to, so a new structure needs to be added + /* A multi-level map: unsigned (warp_id) -> unsigned (pc) -> unsigned (addr) + * -> unsigned (count) */ std::map<unsigned /*warp_id*/, - std::map<unsigned /*pc*/, - std::map<unsigned /*addr*/, unsigned /*count*/>>> + std::map<unsigned /*pc*/, + std::map<unsigned /*addr*/, unsigned /*count*/>>> m_pending_ldgsts; // modifiers virtual void issue(register_set &inst); @@ -1766,8 +1767,8 @@ struct shader_core_stats_pod { unsigned *m_active_tensor_core_lanes; unsigned *m_active_fu_lanes; unsigned *m_active_fu_mem_lanes; - double *m_active_exu_threads; //For power model - double *m_active_exu_warps; //For power model + double *m_active_exu_threads; // For power model + double *m_active_exu_warps; // For power model unsigned *m_n_diverge; // number of divergence occurring in this shader unsigned gpgpu_n_load_insn; unsigned gpgpu_n_store_insn; @@ -1838,56 +1839,41 @@ class shader_core_stats : public shader_core_stats_pod { (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_num_loadqueued_insn = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); - m_num_tex_inst = - (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); + m_num_tex_inst = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_num_INTdecoded_insn = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); - m_num_ialu_acesses = - (double *)calloc(config->num_shader(), sizeof(double)); - m_num_fp_acesses = - (double *)calloc(config->num_shader(), sizeof(double)); - m_num_imul_acesses = - (double *)calloc(config->num_shader(), sizeof(double)); + m_num_ialu_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_fp_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_imul_acesses = (double *)calloc(config->num_shader(), sizeof(double)); m_num_imul24_acesses = (double *)calloc(config->num_shader(), sizeof(double)); m_num_imul32_acesses = (double *)calloc(config->num_shader(), sizeof(double)); m_num_fpmul_acesses = (double *)calloc(config->num_shader(), sizeof(double)); - m_num_idiv_acesses = - (double *)calloc(config->num_shader(), sizeof(double)); + m_num_idiv_acesses = (double *)calloc(config->num_shader(), sizeof(double)); m_num_fpdiv_acesses = (double *)calloc(config->num_shader(), sizeof(double)); - m_num_dp_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_dpmul_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_dpdiv_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_sp_acesses = + m_num_dp_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_dpmul_acesses = (double *)calloc(config->num_shader(), sizeof(double)); - m_num_sfu_acesses = + m_num_dpdiv_acesses = (double *)calloc(config->num_shader(), sizeof(double)); - m_num_tensor_core_acesses = + m_num_sp_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_sfu_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_tensor_core_acesses = (double *)calloc(config->num_shader(), sizeof(double)); m_num_const_acesses = (double *)calloc(config->num_shader(), sizeof(double)); - m_num_tex_acesses = - (double *)calloc(config->num_shader(), sizeof(double)); - m_num_sqrt_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_log_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_sin_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_exp_acesses = - (double*) calloc(config->num_shader(),sizeof(double)); - m_num_mem_acesses = - (double *)calloc(config->num_shader(), sizeof(double)); + m_num_tex_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_sqrt_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_log_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_sin_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_exp_acesses = (double *)calloc(config->num_shader(), sizeof(double)); + m_num_mem_acesses = (double *)calloc(config->num_shader(), sizeof(double)); m_num_sp_committed = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); - m_num_tlb_hits = - (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); + m_num_tlb_hits = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_num_tlb_accesses = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_active_sp_lanes = @@ -1900,8 +1886,7 @@ class shader_core_stats : public shader_core_stats_pod { (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_active_exu_threads = (double *)calloc(config->num_shader(), sizeof(double)); - m_active_exu_warps = - (double *)calloc(config->num_shader(), sizeof(double)); + m_active_exu_warps = (double *)calloc(config->num_shader(), sizeof(double)); m_active_fu_mem_lanes = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_num_sfu_committed = @@ -1916,8 +1901,7 @@ class shader_core_stats : public shader_core_stats_pod { (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); m_non_rf_operands = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); - m_n_diverge = - (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); + m_n_diverge = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); shader_cycle_distro = (unsigned *)calloc(config->warp_size + 3, sizeof(unsigned)); last_shader_cycle_distro = @@ -2153,206 +2137,244 @@ class shader_core_ctx : public core_t { void incload_stat() { m_stats->m_num_loadqueued_insn[m_sid]++; } void incstore_stat() { m_stats->m_num_storequeued_insn[m_sid]++; } - void incialu_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_ialu_acesses[m_sid]=m_stats->m_num_ialu_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_ialu_acesses[m_sid]=m_stats->m_num_ialu_acesses[m_sid]+(double)active_count*latency; + void incialu_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_ialu_acesses[m_sid] = + m_stats->m_num_ialu_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_ialu_acesses[m_sid] = + m_stats->m_num_ialu_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } - void incimul_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_imul_acesses[m_sid]=m_stats->m_num_imul_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_imul_acesses[m_sid]=m_stats->m_num_imul_acesses[m_sid]+(double)active_count*latency; + void incimul_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_imul_acesses[m_sid] = + m_stats->m_num_imul_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_imul_acesses[m_sid] = + m_stats->m_num_imul_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } - void incimul24_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_imul24_acesses[m_sid]=m_stats->m_num_imul24_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_imul24_acesses[m_sid]=m_stats->m_num_imul24_acesses[m_sid]+(double)active_count*latency; + void incimul24_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_imul24_acesses[m_sid] = + m_stats->m_num_imul24_acesses[m_sid] + + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_imul24_acesses[m_sid] = + m_stats->m_num_imul24_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; - m_stats->m_active_exu_warps[m_sid]++; - } - void incimul32_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_imul32_acesses[m_sid]=m_stats->m_num_imul32_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_imul32_acesses[m_sid]=m_stats->m_num_imul32_acesses[m_sid]+(double)active_count*latency; + m_stats->m_active_exu_threads[m_sid] += active_count; + m_stats->m_active_exu_warps[m_sid]++; + } + void incimul32_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_imul32_acesses[m_sid] = + m_stats->m_num_imul32_acesses[m_sid] + + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_imul32_acesses[m_sid] = + m_stats->m_num_imul32_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } - void incidiv_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_idiv_acesses[m_sid]=m_stats->m_num_idiv_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else { - m_stats->m_num_idiv_acesses[m_sid]=m_stats->m_num_idiv_acesses[m_sid]+(double)active_count*latency; + void incidiv_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_idiv_acesses[m_sid] = + m_stats->m_num_idiv_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_idiv_acesses[m_sid] = + m_stats->m_num_idiv_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; - m_stats->m_active_exu_warps[m_sid]++; + m_stats->m_active_exu_threads[m_sid] += active_count; + m_stats->m_active_exu_warps[m_sid]++; } - void incfpalu_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_fp_acesses[m_sid]=m_stats->m_num_fp_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_fp_acesses[m_sid]=m_stats->m_num_fp_acesses[m_sid]+(double)active_count*latency; + void incfpalu_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_fp_acesses[m_sid] = + m_stats->m_num_fp_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_fp_acesses[m_sid] = + m_stats->m_num_fp_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; - m_stats->m_active_exu_warps[m_sid]++; + m_stats->m_active_exu_threads[m_sid] += active_count; + m_stats->m_active_exu_warps[m_sid]++; } - void incfpmul_stat(unsigned active_count,double latency) { - // printf("FP MUL stat increament\n"); - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_fpmul_acesses[m_sid]=m_stats->m_num_fpmul_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_fpmul_acesses[m_sid]=m_stats->m_num_fpmul_acesses[m_sid]+(double)active_count*latency; + void incfpmul_stat(unsigned active_count, double latency) { + // printf("FP MUL stat increament\n"); + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_fpmul_acesses[m_sid] = + m_stats->m_num_fpmul_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_fpmul_acesses[m_sid] = + m_stats->m_num_fpmul_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; - } - void incfpdiv_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_fpdiv_acesses[m_sid]=m_stats->m_num_fpdiv_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else { - m_stats->m_num_fpdiv_acesses[m_sid]=m_stats->m_num_fpdiv_acesses[m_sid]+(double)active_count*latency; + } + void incfpdiv_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_fpdiv_acesses[m_sid] = + m_stats->m_num_fpdiv_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_fpdiv_acesses[m_sid] = + m_stats->m_num_fpdiv_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; - } - void incdpalu_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_dp_acesses[m_sid]=m_stats->m_num_dp_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_dp_acesses[m_sid]=m_stats->m_num_dp_acesses[m_sid]+(double)active_count*latency; + } + void incdpalu_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_dp_acesses[m_sid] = + m_stats->m_num_dp_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_dp_acesses[m_sid] = + m_stats->m_num_dp_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; - m_stats->m_active_exu_warps[m_sid]++; - } - void incdpmul_stat(unsigned active_count,double latency) { - // printf("FP MUL stat increament\n"); - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_dpmul_acesses[m_sid]=m_stats->m_num_dpmul_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_nonsfu(active_count, latency); - }else { - m_stats->m_num_dpmul_acesses[m_sid]=m_stats->m_num_dpmul_acesses[m_sid]+(double)active_count*latency; + m_stats->m_active_exu_threads[m_sid] += active_count; + m_stats->m_active_exu_warps[m_sid]++; + } + void incdpmul_stat(unsigned active_count, double latency) { + // printf("FP MUL stat increament\n"); + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_dpmul_acesses[m_sid] = + m_stats->m_num_dpmul_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_nonsfu(active_count, latency); + } else { + m_stats->m_num_dpmul_acesses[m_sid] = + m_stats->m_num_dpmul_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; - } - void incdpdiv_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_dpdiv_acesses[m_sid]=m_stats->m_num_dpdiv_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else { - m_stats->m_num_dpdiv_acesses[m_sid]=m_stats->m_num_dpdiv_acesses[m_sid]+(double)active_count*latency; + } + void incdpdiv_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_dpdiv_acesses[m_sid] = + m_stats->m_num_dpdiv_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_dpdiv_acesses[m_sid] = + m_stats->m_num_dpdiv_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; - } + } - void incsqrt_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_sqrt_acesses[m_sid]=m_stats->m_num_sqrt_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_sqrt_acesses[m_sid]=m_stats->m_num_sqrt_acesses[m_sid]+(double)active_count*latency; + void incsqrt_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_sqrt_acesses[m_sid] = + m_stats->m_num_sqrt_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_sqrt_acesses[m_sid] = + m_stats->m_num_sqrt_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; - } + } - void inclog_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_log_acesses[m_sid]=m_stats->m_num_log_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_log_acesses[m_sid]=m_stats->m_num_log_acesses[m_sid]+(double)active_count*latency; + void inclog_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_log_acesses[m_sid] = + m_stats->m_num_log_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_log_acesses[m_sid] = + m_stats->m_num_log_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; - } + } - void incexp_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_exp_acesses[m_sid]=m_stats->m_num_exp_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_exp_acesses[m_sid]=m_stats->m_num_exp_acesses[m_sid]+(double)active_count*latency; + void incexp_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_exp_acesses[m_sid] = + m_stats->m_num_exp_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_exp_acesses[m_sid] = + m_stats->m_num_exp_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } - void incsin_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_sin_acesses[m_sid]=m_stats->m_num_sin_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_sin_acesses[m_sid]=m_stats->m_num_sin_acesses[m_sid]+(double)active_count*latency; + void incsin_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_sin_acesses[m_sid] = + m_stats->m_num_sin_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_sin_acesses[m_sid] = + m_stats->m_num_sin_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } - - void inctensor_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_tensor_core_acesses[m_sid]=m_stats->m_num_tensor_core_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_tensor_core_acesses[m_sid]=m_stats->m_num_tensor_core_acesses[m_sid]+(double)active_count*latency; + void inctensor_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_tensor_core_acesses[m_sid] = + m_stats->m_num_tensor_core_acesses[m_sid] + + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_tensor_core_acesses[m_sid] = + m_stats->m_num_tensor_core_acesses[m_sid] + + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } - void inctex_stat(unsigned active_count,double latency) { - if(m_config->gpgpu_clock_gated_lanes==false){ - m_stats->m_num_tex_acesses[m_sid]=m_stats->m_num_tex_acesses[m_sid]+(double)active_count*latency - + inactive_lanes_accesses_sfu(active_count, latency); - }else{ - m_stats->m_num_tex_acesses[m_sid]=m_stats->m_num_tex_acesses[m_sid]+(double)active_count*latency; + void inctex_stat(unsigned active_count, double latency) { + if (m_config->gpgpu_clock_gated_lanes == false) { + m_stats->m_num_tex_acesses[m_sid] = + m_stats->m_num_tex_acesses[m_sid] + (double)active_count * latency + + inactive_lanes_accesses_sfu(active_count, latency); + } else { + m_stats->m_num_tex_acesses[m_sid] = + m_stats->m_num_tex_acesses[m_sid] + (double)active_count * latency; } - m_stats->m_active_exu_threads[m_sid]+=active_count; + m_stats->m_active_exu_threads[m_sid] += active_count; m_stats->m_active_exu_warps[m_sid]++; } void inc_const_accesses(unsigned active_count) { - m_stats->m_num_const_acesses[m_sid]=m_stats->m_num_const_acesses[m_sid]+active_count; + m_stats->m_num_const_acesses[m_sid] = + m_stats->m_num_const_acesses[m_sid] + active_count; } void incsfu_stat(unsigned active_count, double latency) { m_stats->m_num_sfu_acesses[m_sid] = - m_stats->m_num_sfu_acesses[m_sid] + (double)active_count*latency; + m_stats->m_num_sfu_acesses[m_sid] + (double)active_count * latency; } void incsp_stat(unsigned active_count, double latency) { m_stats->m_num_sp_acesses[m_sid] = - m_stats->m_num_sp_acesses[m_sid] + (double)active_count*latency; + m_stats->m_num_sp_acesses[m_sid] + (double)active_count * latency; } void incmem_stat(unsigned active_count, double latency) { if (m_config->gpgpu_clock_gated_lanes == false) { m_stats->m_num_mem_acesses[m_sid] = - m_stats->m_num_mem_acesses[m_sid] + (double)active_count*latency + + m_stats->m_num_mem_acesses[m_sid] + (double)active_count * latency + inactive_lanes_accesses_nonsfu(active_count, latency); } else { m_stats->m_num_mem_acesses[m_sid] = - m_stats->m_num_mem_acesses[m_sid] + (double)active_count*latency; + m_stats->m_num_mem_acesses[m_sid] + (double)active_count * latency; } } void incexecstat(warp_inst_t *&inst); |